SPECIFICATIONS FOR LIQUID CRYSTAL DISPLAY MODULE

MODEL NO: 19264-05

3. OPERATING PRINCIPALS AND METHODS

3. OPERATING PRINCIPALS AND METHODS

3.1 LCD Controller Display and Control Functions (KS0108 Controller)

3.1 LCD Controller Display and Control Functions (KS0108 Controller)

■ I/O Buffer

■ I/O Buffer

Input buffer controls the status between the enable and disable of chip. Unless the CS1 or CS2 is in active mode,

input or output of data and instruction do not execute. Therefore internal state is not change. But RSTB can operate

regardless of CS1 and CS2.

Input buffer controls the status between the enable and disable of chip. Unless the CS1 or CS2 is in active mode,

input or output of data and instruction do not execute. Therefore internal state is not change. But RSTB can operate

regardless of CS1 and CS2.

■ Input Register

■ Input Register

Input register is provided to interface with MPU which is different operating frequency. Input register stores the

data temporarily before writing it into display data RAM.

Input register is provided to interface with MPU which is different operating frequency. Input register stores the

data temporarily before writing it into display data RAM.

When CS1 or CS2 is in the active mode, R/W and RS select the input register. The data from MPU is written into

input register and then write it into display data RAM. Data is latched when falling of the E signal and written

automatically into the display data RAM by internal operation.

When CS1 or CS2 is in the active mode, R/W and RS select the input register. The data from MPU is written into

input register and then write it into display data RAM. Data is latched when falling of the E signal and written

automatically into the display data RAM by internal operation.

■ Output Register

■ Output Register

Output register stores the data temporarily from display data RAM when CS1 or CS2 is in active mode and R/W

and RS = H. Stored data in display data RAM is latched in output register. When CS1 or CS2 is in active mode and R/W =

H, RS = L, status data (busy check) can be read out.

Output register stores the data temporarily from display data RAM when CS1 or CS2 is in active mode and R/W

and RS = H. Stored data in display data RAM is latched in output register. When CS1 or CS2 is in active mode and R/W =

H, RS = L, status data (busy check) can be read out.

To read the contents of display data RAM, twice access of read instruction is needed. In first access, data in

display data RAM is latched into output register. In second access, MPU can read data which is latched. That is, to read the

data in display data RAM, it needs dummy read. But status read does not need dummy read.

To read the contents of display data RAM, twice access of read instruction is needed. In first access, data in

display data RAM is latched into output register. In second access, MPU can read data which is latched. That is, to read the

data in display data RAM, it needs dummy read. But status read does not need dummy read.

RS

RS

R/W

R/W

Function

Function

0

0

Instruction

1

Status read (busy check)

1

0

Data write (from input register to display data RAM)

1

Data read (from display data RAM to output register)

■ Reset

System reset can be initialized by setting RST terminal at low level when turning power on, receiving instruction

from MPU. When RST becomes low, following procedure is occurred.

1. Display off

2. Display start line register become set by 0. ( Z-address 0 )

While RST is low level, no instruction except status read can be accepted. Reset status appears at DB4. After DB4

is low, any instruction can be accepted.

The Conditions of power supply at initial power up are shown in table 1.

Table 1. Power Supply Initial Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

Reset time

tRST

1.0

---

---

us

Rise time

tr

---

---

200

ns

PACIFIC DISPLAY DEVICES

06.27.2003

11

tRST

0.7VDD

0.3VDD

tr

4.5V

VDD

RST