HC05V12GRSSLASHD datasheet(52/240 Pages) NXP

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Interrupts

General Release Specification

MC68HC05V12 — Rev. 1.0

Interrupts

4.2 Introduction

The MCU can be interrupted eight different ways:

1. Non-Maskable Software Interrupt Instruction (SWI)

2. External Asynchronous Interrupt (IRQ)

3. External Interrupt via IRQ on PC0–PC7 (IRQ)

4. Internal 16-Bit Timer Interrupt (TIMER)

5. Internal BDLC Interrupt (BDLC)

6. Internal Serial Peripheral Interface Interrupt (SPI)

7. Internal 8-Bit Timer Interrupt (CTIMER)

8. Internal Gauge Interrupt (GAUGE)

4.3 CPU Interrupt Processing

Interrupts cause the processor to save register contents on the stack

and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike

RESET, hardware interrupts do not cause the current instruction

execution to be halted, but are considered pending until the current

instruction is complete.

If interrupts are not masked (I bit in the CCR is clear) and the

corresponding interrupt enable bit is set, then the processor will proceed

with interrupt processing. Otherwise, the next instruction is fetched and

executed. If an interrupt occurs, the processor completes the current

instruction, then stacks the current CPU register states, sets the I bit to

inhibit further interrupts, and finally checks the pending hardware

interrupts. If more than one interrupt is pending after the stacking

operation, the interrupt with the highest vector location shown in

Table 4-1 will be serviced first. The SWI is executed the same as any

other instruction, regardless of the I-bit state.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC05V12GRS/D Datasheet(PDF) 52 Page - NXP Semiconductors