UPD301A

DS00002838B-page 16

 2018-2019 Microchip Technology Inc.

4.0

FUNCTIONAL DESCRIPTIONS

This section provides functional descriptions of the following:

• Serial Peripheral Interface (SPI)

• Power States

• Cable Plug Orientation and Detection

• Baseband CC Interface (BCI)

• Power Delivery MAC

• Supported Power Delivery (PD) Functionality

4.1

Serial Peripheral Interface (SPI)

The UPD301A integrates a SPI master/slave controller which includes the following features:

• • Full-duplex, four-wire interface (SPI_MISO, SPI_MOSI, SPI_SCK, SPI_SS)

• • Single-buffered transmitter, double-buffered receiver

• • Master operation:

- – Serial clock speed, fSCK=1/tSCK(Note 4-1)

- – 8-bit clock generator

• • Slave operation:

- – Serial clock speed, fSCK=1/tSSCK(Note 4-1)

- – Optional 8-bit address match operation

Note 4-1

For tSCK and tSSCK values, refer to Section 5.6.2, "SPI Timing"

The SPI is a high-speed synchronous data transfer interface which allows high-speed communication between the

device and peripheral devices. The SPI can operate as a master or slave. As a master, the SPI initiates and controls all

data transactions. The SPI is single buffered for transmitting and double buffered for receiving.

When transmitting data, a Data register is loaded with the next character to be transmitted during the current transmis-

sion. When receiving, the data is transferred to the two-level receive buffer, and the receiver is ready for a new character.

The SPI transaction format is shown in Figure 4-1. Each transaction can contain one or more characters. The character

size is configurable, and can be either 8 or 9 bits.

The SPI master pulls the slave select line (SPI_SS) of the desired slave low to initiate a transaction. The master and

slave prepare data to send via their respective shift registers, and the master generates the serial clock on the SPI_SCK

line.

Data is always shifted from master to slave on the Master Output Slave Input line (SPI_MOSI); data is shifted from slave

to master on the Master Input Slave Output line (SPI_MISO).

Each time character is shifted out from the master, a character will be shifted out from the slave simultaneously. To signal

the end of a transaction, the master will pull the SPI_SS line high.

FIGURE 4-1:

SPI TRANSACTION FORMAT

SPI_SS

SPI_MOSI/

SPI_MISO