8.2.1 Design Requirements

Table 8-1 shows the design parameters for this application.

Table 8-1. Design Parameters

PARAMETER

EXAMPLE VALUE

Input voltage range

4.2 V to 17 V

Output voltage

1.05 V

Transient response, 1.5-A load step

ΔVout = ±5%

Input ripple voltage

100 mV

Output ripple voltage

20 mV

Output current rating

3 A

Operating frequency

600 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the FB pin. TI recommends to use 1%

tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT.

To improve efficiency at very light loads, consider using larger value resistors. Too high of resistance is more

susceptible to noise and voltage errors from the FB input current are more noticeable.

(3)

8.2.2.2 Output Filter Selection

The LC filter used as the output filter has a double pole at Equation 4. In this equation, COUT must use its

effective value after derating, not its nominal value.

P

OUT

OUT

1

f

2

L

C

S

u

(4)

For any control topology that is compensated internally, there is a range of the output filter it can support. At low

frequency, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the

device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40 dB per

decade rate and the phase drops has a 180 degree drop. The internal ripple generation network introduces a

high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per decade and leads the 90 degree

phase boost. The internal ripple injection high-frequency zero is about 41 kHz. TI recommends the inductor

and capacitor selected for the output filter that the double pole is located about 20 kHz, so that the phase

boost provided by this high-frequency zero provides adequate phase margin for the stability requirement. For

higher than 2-V output voltage, TI suggests to add a CFF cap to increase the bandwidth and phase margin.

The suggested CFF range is 10 pF to 100 pF. The crossover frequency of the overall system must usually be

targeted to be less than one-third of the switching frequency.

Table 8-2. Recommended Component Values

OUTPUT

VOLTAGE

(V)

R1 (kΩ)

R2 (kΩ)

Min L(uH)

TYP L (uH)

Max L(uH)

Min

Cout(uF)

Typ Cout(uF)

Max

Cout(uF)

Typ CFF(pF)

0.8

3.33

10.0

1

1.5

2.2

22

44

110

-

1.05

7.5

10.0

1.2

2.2

3.3

22

44

110

-

2.5

95.0

30.0

2.2

3.3

4.7

22

44

110

10

3.3

135.0

30.0

3.3

4.7

6.8

22

44

110

18

TPS563203, TPS563206

SLUSEZ4 – MARCH 2023

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