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DFE252012PD-2R2M Datasheet(PDF) 40 Page - Texas Instruments |
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DFE252012PD-2R2M Datasheet(HTML) 40 Page - Texas Instruments |
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40 / 54 page ![]() • Increased EMI radiation • Noise sensitivity See Figure 9-79 for the recommended layout of the TPS629211-Q1, which is designed for common external ground connections. The input capacitor must be placed as close as possible between the VIN and GND pin of the TPS629211-Q1. Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for wires with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to the IC pins and parallel wiring over long distances as well as narrow traces must be avoided. Loops that conduct an alternating current must outline an area as small as possible, as this area is proportional to the energy radiated. Sensitive nodes like FB and VOS must be connected with short wires and not nearby high dv/dt signals (for example, SW). As they carry information about the output voltage, they also must be connected as close as possible to the actual output voltage (at the output capacitor). The FB resistors, R1 and R2, must be kept close to the IC and connect directly to those pins and the system ground plane. The same applies for the S-CONFIG/ MODE and VSET programming resistors. The package uses the pins for power dissipation. Thermal vias on the VIN, GND, and SW pins help to spread the heat through the PCB. In case any of the digital inputs (EN or S-CONF/MODE pins) must be tied to the input supply voltage at VIN, the connection must be made directly at the input capacitor as indicated in the schematics. The recommended layout is implemented on the EVM and shown in the TPS629211-Q1EVM User's Guide. 9.5.2 Layout Example GND VIN EN S-CONFIG VOS PG FB SW GND VIN VOUT Figure 9-79. TPS629211-Q1 Layout 9.5.3 Thermal Considerations Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power- dissipation limits of a given component. The following are basic approaches for enhancing thermal performance: • Improving the power dissipation capability of the PCB design (for example, increasing copper thickness, thermal vias, number of layers) • Introducing airflow in the system TPS629211-Q1 SLVSGD0A – MARCH 2022 – REVISED MARCH 2023 www.ti.com 40 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TPS629211-Q1 |
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