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ST25R3912 Datasheet(PDF) 77 Page - STMicroelectronics |
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ST25R3912 Datasheet(HTML) 77 Page - STMicroelectronics |
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77 / 130 page ![]() DS11794 Rev 9 77/130 ST25R3912 111 1.3.8 ISO14443B and FeliCa settings register Address: 07h Type: RW Table 30. ISO14443B and FeliCa settings register(1) Bit Name Default Function Comments 7tr1_1 0 Refer to Table 31 - 6tr1_0 0 5 no_sof 0 1: No SOF PICC to PCD According to ISO14443-3 chapter 7.10.3.3 Support of B’ 4 no_eof 0 1: No EOF PICC to PCD According to ISO14443-3 chapter 7.10.3.3 3eof_12 0 0: PICC EOF 10 to 11 etu 1: PICC EOF 10 to 12 etu Support of B(2) 2 phc_th 0 1: Increased tolerance of phase change detection - 1 f_p1 0 00: 48 01: 64 10: 80 11: 96 FeliCa preamble length (valid also for NFCIP-1 active communication bit rates 242 and 484 kb/s) 0f_p0 0 1. Default setting takes place at power-up and after Set default command. 2. Detection of EOF requires larger tolerance range for bit rates with only one sub-carrier frequency period per bit (fc / 16 and higher). Due to this it is not possible to distinguish between EOF with 11 and 12 etu and setting this bit has no impact on EOF detection. Table 31. Minimum TR1 codings tr1_1 tr1_0 Minimum TR1 for a PICC to PCD bit rate fc / 128 >fc / 128 0 0 80 / fs 80 / fs 0 1 64 / fs 32 / fs 1 0 Not used Not used 1 1 Not used Not used |
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