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ICS9LPRS477C Datasheet(PDF) 12 Page - Renesas Technology Corp |
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ICS9LPRS477C Datasheet(HTML) 12 Page - Renesas Technology Corp |
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12 / 25 page  IDT® Programmable System Clock Chip for ATI RD790-K8TM Based Systems 1393—01/28/14 9LPRS477C Programmable System Clock Chip for ATI RD790 - K8TM based Systems 12 SMBus Table: WD Timer Safe Frequency Control Register Byte 10 Name Control Function Type 0 1 Default Bit 7 SWD2 WD Soft Alarm Timer Bit 2 RW 1 Bit 6 SWD1 WD Soft Alarm Timer Bit 1 RW 1 Bit 5 SWD0 WD Soft Alarm Timer Bit 0 RW 1 Bit 4 WD SF4 RW 0 Bit 3 WD SF3 RW 1 Bit 2 WD SF2 RW 1 Bit 1 WD SF1 RW 1 Bit 0 WD SF0 RW 1 SMBus Table: Byte Count Register Byte 11 Name Control Function Type 0 1 Default Bit 7 0 Bit 6 0 Bit 5 BC5 Byte Count bit 5 (MSB) RW 0 Bit 4 BC4 Byte Count bit 4 RW 0 Bit 3 BC3 Byte Count bit 3 RW 1 Bit 2 BC2 Byte Count bit 2 RW 1 Bit 1 BC1 Byte Count bit 1 RW 1 Bit 0 BC0 Byte Count bit 0 (LSB) RW 1 SMBus Table: M/N Programming Enable and I/O Vout Control Register Byte 12 Name Control Function Type 0 1 Default Bit 7 CPU M/N En CPU PLL M/N Prog. Enable RW M/N Prog. Disabled M/N Prog. Enabled 0 Bit 6 SRC M/N En SRC M/N Prog.Enable RW M/N Prog. Disabled M/N Prog. Enabled 0 Bit 5 ATIG M/N En ATIG M/N Prog. Enable RW M/N Prog. Disabled M/N Prog. Enabled 0 Bit 4 SB_SRC M/N En SB_SRC M/N Prog. Enable RW M/N Prog. Disabled M/N Prog. Enabled 0 Bit 3 SEL_OC_MODE readback OC MODE Select R PCIE Gen2 Mode PCIE Gen1 Mode Latch Bit 2 IO_VOUT2 IO Output Voltage Select (Most Significant Bit) RW 1 Bit 1 IO_VOUT1 IO Output Voltage Select RW 0 Bit 0 IO_VOUT0 IO Output Voltage Select (Least Significant Bit) RW 1 Bytes 13/14 are reserved SMBus Table:Test Mode Register Byte 15 Name Control Function Type 0 1 Default Bit 7 Test_Sel Selects Test Mode RW Normal mode All ouputs are REF/N 0 Bit 6 SB_SRC Source SB_SRC Source Selection RW SB_SRC PLL SRC PLL 1 Bit 5 ATIG PLL ATIG PLL DOC pin control RW DOC0 DOC1 0 Bit 4 CPU PLL CPU PLL DOC pin control RW DOC0 DOC1 0 Bit 3 SRC PLL SRC PLL DOC pin control RW DOC0 DOC1 0 Bit 2 ATIG PLL ATIG PLL DOC0 2 pin control RW Disable Enable 0 Bit 1 CPU PLL CPU PLL DOC0 2 pin control RW Disable Enable 0 Bit 0 SRC PLL SRC PLL DOC0 2 pin control RW Disable Enable 0 SMBus Table: CPU PLL Frequency Control Register Byte 16 Name Control Function Type 0 1 Default Bit 7 N Div2 N Divider Prog bit 2 RW X Bit 6 N Div1 N Divider Prog bit 1 RW X Bit 5 M Div5 RW X Bit 4 M Div4 RW X Bit 3 M Div3 RW X Bit 2 M Div2 RW X Bit 1 M Div1 RW X Bit 0 M Div0 RW X Watch Dog Safe Freq Programming bits M Divider Programming bits The decimal representation of M and N Divider in Byte 16 and 17 w ill configure the VCO frequency. Default at pow er up = Byte 3 Rom table. See M/N Caculation Tables for VCO frequency formulas. Determines the number of bytes that are read back from the device. Default is 0F hex. These bits represent the number of Watch Dog Time Base Units that pass before the Watch Alarm expires. Default is 7 X 290ms = 2s. Reserved These bits configure the safe frequency that the device returns to if the Watchdog Timer expires. The value show here corresponds to the pow er up default of the device. See the various Frequency Select Tables for the exact frequencies. See Table 5: V_IO Selection (Default is 0.8V) Reserved |
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