IDT®

Programmable System Clock Chip for ATI RD790-K8TM Based Systems

1393—01/28/14

9LPRS477C

Programmable System Clock Chip for ATI RD790 - K8TM based Systems

17

SMBUS Table: SRC PLL DOC 3 N programming Register (1 pin control : DOC = 1; 2 pin control : DOC [0:1] = 11)

Byte

40

Name

Control Function

Type

0

1

Default

Bit 7

N Div10

RW

X

Bit 6

N Div9

RW

X

Bit 5

N Div8

RW

X

Bit 4

N Div7

RW

X

Bit 3

N Div6

RW

X

Bit 2

N Div5

RW

X

Bit 1

N Div4

RW

X

Bit 0

N Div3

RW

X

SMBus Table: ATIG PLL Spread Spectrum Control Register

Byte

41

Name

Control Function

Type

0

1

Default

Bit 7

SSP7

RW

X

Bit 6

SSP6

RW

X

Bit 5

SSP5

RW

X

Bit 4

SSP4

RW

X

Bit 3

SSP3

RW

X

Bit 2

SSP2

RW

X

Bit 1

SSP1

RW

X

Bit 0

SSP0

RW

X

SMBus Table: ATIG PLL Spread Spectrum Control Register

Byte

42

Name

Control Function

Type

0

1

Default

Bit 7

SSP15

RW

X

Bit 6

SSP14

RW

X

Bit 5

SSP13

RW

X

Bit 4

SSP12

RW

X

Bit 3

SSP11

RW

X

Bit 2

SSP10

RW

X

Bit 1

SSP9

RW

X

Bit 0

SSP8

RW

X

N Divider Programming Byte20

bit(7:0) and Byte19 bit(7:6)

The decimal representation of M and N Divider in Byte 21 and 37

w ill configure the VCO frequency. Default at pow er up = Byte

4 Rom table. See M/N Caculation Tables for VCO frequency

formulas.

Spread Spectrum Programming

b(15:8)

These bits set the ATIG spread pecentage.Please contact IDT

for the appropriate values.

Spread Spectrum Programming

b(7:0)

These bits set the ATIG spread pecentage.Please contact IDT

for the appropriate values.