IDT®

Programmable System Clock Chip for ATI RD790-K8TM Based Systems

1393—01/28/14

9LPRS477C

Programmable System Clock Chip for ATI RD790 - K8TM based Systems

18

Absolute Maximum Rating

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

3.3V Core Supply Voltage

VDDxxx

-

3.3

GND + 3.9V

V

1

Storage Temperature

Ts

-

-65

150

°

C1

Ambient Operating Temp

Tambient

-

0

70

°C

1

Case Temperature

Tcase

-

115

°C

1

Input ESD protection HBM

ESD prot

-

2000

V

1

1

Guaranteed by design and characterization, not 100% tested in production.

Electrical Characteristics - Input/Supply/Common Output Parameters

PARAMETER

SYMBOL

CONDITIONS*

MIN

TYP

MAX

UNITS

Notes

3.3V Core Supply Voltage

VDDxxx

-

3.135

3.3

3.465

V

1

Input High Voltage

V

IH

VDD = 3.3 V +/-5%

2

V

DD + 0.3

V

1

Input Low Voltage

V

IL

VDD = 3.3 V +/-5%

V

SS - 0.3

0.8

V

1

Input High Current

I

IH

V

IN = VDD

-5

5

uA

1

I

IL1

V

IN = 0 V; Inputs w ith no pull-up

resistors

-5

uA

1

I

IL2

V

IN = 0 V; Inputs w ith pull-up

resistors

-200

uA

1

Low Threshold Input-

High Voltage

V

IH_FS

VDD = 3.3 V +/-5%

0.7

V

DD + 0.3

V

1

Low Threshold Input-

Low Voltage

V

IL_FS

VDD = 3.3 V +/-5%

V

SS - 0.3

0.35

V

1

Operating Current

I

DD3.3OP

all outputs driven

225

mA

1

Pow erdow n Current

I

DD3.3PD

all diff pairs low /low

12

mA

1

Input Frequency

F

i

VDD = 3.3 V +/-5%

14.31818

MHz

2

Pin Inductance

L

pin

7nH

1

C

IN

Logic Inputs

5

pF

1

C

OUT

Output pin capacitance

6

pF

1

C

INX

X1 & X2 pins

5

pF

1

Clk Stabilization

T

STAB

From VDD Pow er-Up or de-

assertion of PD to 1st clock

1.8

ms

1

Modulation Frequency

Triangular Modulation

30

33

kHz

1

Tdrive_PD

CPU output enable after

PD de-assertion

300

us

1

Tfall_PD

PD fall time of

5

ns

1

Trise_PD

PD rise time of

5

ns

1

SMBus Voltage

V

DDSMB

2.7

5.5

V

1

Low -level Output Voltage

V

OLSMB

@ I

PULLUP

0.4

V

1

Current sinking at

V

OL = 0.4 V

I

PULLUPSMB

46

mA

1

SMBCLK/SMBDAT

Clock/Data Rise Time

T

RSMB

(Max VIL - 0.15) to

(Min VIH + 0.15)

1000

ns

1

SMBCLK/SMBDAT

Clock/Data Fall Time

T

FSMB

(Min VIH + 0.15) to

(Max VIL - 0.15)

300

ns

1

*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%

1

Guaranteed by design and characterization, not 100% tested in production.

Input Low Current

Input Capacitance

2

Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.