AT25SF161 datasheet(21/51 Pages) RENESAS

21 / 51 page

AT25SF161

DS-25SF161–

046I–02/2021

in the Status Register will then be reset back to the logical "0" state to indicate the program or erase operation is no

longer suspended. In addition, the RDY/BSY bit in the Status Register will indicate that the device is busy performing a

program or erase operation. The complete opcode must be clocked into the device before the CS pin is deasserted, and

the CS pin must be deasserted on a byte boundary (multiples of eight bits). Otherwise, no resume operation will perform.

During a simultaneous Erase Suspend/Program Suspend condition, issuing the Program/Erase Resume command will

result in the program operation resuming first. After the program operation has been completed, the Program/Erase

Resume command must be issued again in order for the erase operation to be resumed.

While the device is busy resuming a program or erase operation, any attempts at issuing the Program/Erase Suspend

command will be ignored. Therefore, if a resumed program or erase operation needs to be subsequently suspended

again, the system must either wait the entire tRES time before issuing the Program/Erase Suspend command, or it must

check the status of the RDY/BSY bit or the SUS bit in the Status Register to determine if the previously suspended

program or erase operation has resumed.

Figure 7-6. Program/Erase Resume.

Protection Commands and Features

8.1

Write Enable (06h)

The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1” state.

The WEL bit must be set before a Byte/Page Program, Erase, Program Security Register Pages, Erase Security Register

Pages or Write Status Register command can be executed. This makes the issuance of these commands a two step

process, thereby reducing the chances of a command being accidentally or erroneously executed. If the WEL bit in the

Status Register is not set prior to the issuance of one of these commands, then the command will not be executed.

To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h must be clocked into the

device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored.

When the CS pin is deasserted, the WEL bit in the Status Register will be set to a logical “1”. The complete opcode must

be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an byte boundary

(multiples of eight bits); otherwise, the device will abort the operation and the WEL bit state will not change.

Figure 8-1. Write Enable

SCK

MSB

11 1010

OPCODE

GH-

MPEDANCE

AT25SF161 Datasheet(PDF) 21 Page - Renesas Technology Corp