DA16200 datasheet(7/154 Pages) RENESAS

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

7 of 153

Figure 15: Memory Map: Peripherals .................................................................................................. 37

Figure 16: Pulse Counter Block Diagram ............................................................................................ 40

Figure 17: DMA1 Controller Block Diagram ........................................................................................ 42

Figure 18: DMA1 State Machine ......................................................................................................... 43

Figure 19: DMA2 Block Diagram ......................................................................................................... 45

Figure 20: Watchdog Timer Block Diagram ........................................................................................ 46

Figure 21: Watchdog Operation Flow Diagram ................................................................................... 47

Figure 22: Clock Tree Diagram ........................................................................................................... 48

Figure 23: QSPI Master Block Diagram .............................................................................................. 51

Figure 24: QSPI Master Timing Diagram (Mode 0)............................................................................. 51

Figure 25: SPI Master Timing Diagram (Mode 0)................................................................................ 52

Figure 26: SPI Slave Block Diagram ................................................................................................... 53

Figure 27: 8-byte Control Type............................................................................................................ 53

Figure 28: 4-byte Control Type............................................................................................................ 53

Figure 29: SPI Slave Timing Diagram ................................................................................................. 55

Figure 30: SDIO Slave Block Diagram ................................................................................................ 56

Figure 31: SDIO Slave Timing Diagram .............................................................................................. 57

Figure 32: SDIO Pull-up Resistor ........................................................................................................ 57

Figure 33: I2C Master Timing Diagram ............................................................................................... 58

Figure 34: I2C Slave Timing Diagram ................................................................................................. 60

Figure 35: I2C Pull-up Resistor ........................................................................................................... 61

Figure 36: SD/eMMC Block Diagram .................................................................................................. 62

Figure 37: SD/eMMC Master Timing Diagram .................................................................................... 62

Figure 38: I2S Block Diagram.............................................................................................................. 63

Figure 39: I2S Clock Scheme.............................................................................................................. 64

Figure 40: I2S Timing Diagram ........................................................................................................... 65

Figure 41: Left Justified Mode Timing Diagram................................................................................... 65

Figure 42: Right Justified Mode Timing Diagram ................................................................................ 65

Figure 43: I2S Transmit Timing Diagram ............................................................................................ 65

Figure 44: I2S Receive Timing Diagram ............................................................................................. 65

Figure 45: ADC Control Block Diagram............................................................................................... 67

Figure 46: 12-bit ADC Timing Diagram ............................................................................................... 67

Figure 47: Antenna Switching Internal Block Diagram ........................................................................ 69

Figure 48: Antenna Switching Timing Diagram ................................................................................... 70

Figure 49: DA16200 UART Block Diagram ......................................................................................... 71

Figure 50: Serial Data Format ............................................................................................................. 72

Figure 51: Receiver Serial Data Sampling Points ............................................................................... 72

Figure 52: UARTTXDOE Output Signal for UART RS-485 ................................................................. 72

Figure 53: UART Hardware Flow Control............................................................................................ 73

Figure 54: PWM Block Diagram .......................................................................................................... 75

Figure 55: PWM Timing Diagram ........................................................................................................ 76

Figure 56: JTAG Timing Diagram........................................................................................................ 76

Figure 57: Bluetooth Coexistence Interface ........................................................................................ 78

Figure 58: Bluetooth Coexistence Interface (Antenna Switch)............................................................ 79

Figure 59: PIN MUX Table .................................................................................................................. 94

Figure 60: PIN MUX Table (Continued) .............................................................................................. 95

Figure 61: Typical Application

– QFN, 3.3 V Flash ........................................................................... 133

Figure 62: Typical Application

– QFN, 1.8 V Flash ........................................................................... 135

Figure 63: Typical Application

– fcCSP, 1.8 V Flash, Normal Power Mode...................................... 137

Figure 64: Typical Application

– fcCSP, 1.8 V Flash, Low Power Mode........................................... 139

Figure 65: DA16200 48-Pin QFN Package ....................................................................................... 141

Figure 66: DA16200 72-Pin fcCSP Package..................................................................................... 141

Figure 67: Top View .......................................................................................................................... 142

Figure 68: Bottom View ..................................................................................................................... 142

Figure 69: Side View ......................................................................................................................... 142

Figure 70: DA16200 48-Pin QFN Package Dimensions ................................................................... 142

Figure 71: Top View .......................................................................................................................... 143

Figure 72: Bottom View ..................................................................................................................... 143

Figure 73: Side View ......................................................................................................................... 143

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