ISL72027SEH

FN8763 Rev 3.00

Page 7 of 19

August 16, 2016

DRIVER SWITCHING CHARACTERISTICS

Propagation Delay LOW to HIGH tPDLH1

RS = 0V, Figure 13

Full

-

75

150

ns

Propagation Delay LOW to HIGH tPDLH2

RS = 10kΩ, Figure 13

Full

-

520

850

ns

Propagation Delay LOW to HIGH tPDLH3

RS = 50kΩ, Figure 13

Full

-

850

1400

ns

Propagation Delay HIGH to LOW tPDHL1

RS = 0V, Figure 13

Full

-

80

155

ns

Propagation Delay HIGH to LOW tPDHL2

RS = 10kΩ, Figure 13

Full

-

460

800

ns

Propagation Delay HIGH to LOW tPDHL3

RS = 50kΩ, Figure 13

Full

-

725

1300

ns

Output Skew

tSKEW1

RS = 0V, (|tPHL - tPLH|), Figure 13

Full

-

5

50

ns

Output Skew

tSKEW2

RS = 10kΩ, (|tPHL - tPLH|), Figure 13

Full

-

60

510

ns

Output Skew

tSKEW3

RS = 50kΩ, (|tPHL - tPLH|), Figure 13

Full

-

110

800

ns

Output Rise Time

tr1

RS = 0V, (fast speed)

Figure 13

Full

20

55

100

ns

Output Fall Time

tf1

Full

10

25

75

ns

Output Rise Time

tr2

RS = 10kΩ, (medium speed - 250Kbps)

Figure 13

Full

200

400

780

ns

Output Fall Time

tf2

Full

175

300

500

ns

Output Rise Time

tr3

RS = 50kΩ, (slow speed - 125Kbps)

Figure 13

Full

400

700

1400

ns

Output Fall Time

tf3

Full

300

650

1000

ns

Total Loop Delay, Driver Input to

Receiver Output, Recessive to

Dominant

t(LOOP1)

RS = 0V, Figure 16

Full

-

115

210

ns

RS = 10kΩ, Figure 16

Full

-

550

875

ns

RS = 50kΩ, Figure 16

Full

-

850

1400

ns

Total Loop Delay, Driver Input to

Receiver Output, Dominant to

Recessive

t(LOOP2)

RS = 0V, Figure 16

Full

-

130

270

ns

RS = 10kΩ, Figure 16

Full

-

500

825

ns

RS = 50kΩ, Figure 16

Full

-

750

1300

ns

Listen to Valid Dominant Time

tL-DOM)

Figure 17

Full

-

5

15

us

RECEIVER SWITCHING CHARACTERISTICS

Propagation Delay LOW to HIGH tPLH

Figure 14

Full

-

50

110

ns

Propagation Delay HIGH to LOW tPHL

Figure 14

Full

-

50

110

ns

Rx Skew

tSKEW1

|(tPHL - tPLH)|, Figure 14

Full

-

2

35

ns

Rx Rise Time

tr

Figure 14

Full

-

2

-

ns

Rx Fall Time

tf

Figure 14

Full

-

2

-

ns

VREF/RS PIN CHARACTERISTICS

VREF Pin Voltage

VREF

-5µA<IREF<5µA

Full

0.45xVCC

1.60

0.55xVCC

V

-50µA<IREF<50µA

Full

0.4xVCC

1.6

0.6xVCC

V

RS Pin Input Current

IRS(H)

RS = 0.75 x VCC

Full

-10.0

-0.2

-

µA

IRS(L)

VRS = 0V

Full

-450

-125

0

µA

NOTES:

5. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise

specified.

6. Parameters with MIN and/or MAX limits are 100% tested at -55°C, +25°C and +125°C, unless otherwise specified.

7. Typical values are at 3.3V. Parameters with a single entry in the “TYP” column apply to 3.3V. Typical values shown are not guaranteed.

8. Parameter included in functional testing.

Electrical Specifications Test Conditions: VCC = 3V to 3.6V; Typicals are at TA = +25°C (Note 7); unless otherwise specified (Note 5).

Boldface limits apply across the operating temperature range, -55°C to +125°C or across a total ionizing dose of 75krad(Si) at +25°C with exposure at

a low dose rate of <10mrad(Si)/s. (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

TEMP

(°C)

MIN

(Note 6)

TYP

(Note 7)

MAX

(Note 6)UNIT