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ISL72027SEHF/PROTO Datasheet(PDF) 10 Page - Renesas Technology Corp |
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ISL72027SEHF/PROTO Datasheet(HTML) 10 Page - Renesas Technology Corp |
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10 / 19 page  ISL72027SEH FN8763 Rev 3.00 Page 10 of 19 August 16, 2016 FIGURE 16A. TOTAL LOOP DELAY TEST CIRCUIT FIGURE 16B. TOTAL LOOP DELAY MEASUREMENT POINTS FIGURE 16. TOTAL LOOP DELAY FIGURE 17A. LISTEN TO VALID DOMINANT TIME CIRCUIT FIGURE 17B. LISTEN TO VALID DOMINANT TIME MEASUREMENT POINTS FIGURE 17. LISTEN TO VALID DOMINANT TIME FIGURE 18A. OUTPUT SHORT-CIRCUIT CURRENT CIRCUIT FIGURE 18B. OUTPUT SHORT-CIRCUIT CURRENT WAVEFORMS FIGURE 18. OUTPUT SHORT-CIRCUIT Test Circuits and Waveforms (Continued) 0Ω,10kΩ,50kΩ 60Ω CAN H CAN L GND RS VREF D R VO VIN 15pF ±20% VIN = 125kHz, Duty Cycle 50%, tr = tf ≤ 6ns ±1% FLOAT t(LOOP2) 50% 50% 50% 50% t(LOOP1) VIN VO VCC 0V VOH VOL D VREF RS R CAN_L CAN_H GND VOD 60Ω VIN 15pF ±20% FLOAT ±1% VO VIN = 125kHz, 0V to VCC, Duty Cycle 50%, tr = tf ≤ 6ns 50% VIN VO VCC 0V VOH VOL t L - DOM 50% D CANH CANL GND GND + - VIN = -7V OR 12V IO(SRT) IO(SRT) |IO(SRT)| 0A 0V VIN VIN 12V -7V 10ms |
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