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ISLA112P25MREP Datasheet(PDF) 2 Page - Renesas Technology Corp |
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ISLA112P25MREP Datasheet(HTML) 2 Page - Renesas Technology Corp |
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2 / 29 page ![]() ISLA112P25M FN7646 Rev 1.00 Page 2 of 29 November 17, 2011 Pin Configuration ISLA112P25MREP (72 LD QFN) TOP VIEW Pin Descriptions PIN NUMBER LVDS [LVCMOS] NAME LVDS [LVCMOS] FUNCTION SDR MODE DDR MODE COMMENTS 1, 6, 12, 19, 24, 71 AVDD 1.8V Analog Supply 2, 3, 4, 5, 13, 14, 17, 18, 28, 29, 30, 31 DNC Do Not Connect 7, 8, 11, 72 AVSS Analog Ground 9, 10 VINN, VINP Analog Input Negative, Positive 15 VCM Common Mode Output 16 CLKDIV Tri-Level Clock Divider Control 72 71 70 69 68 67 66 65 64 63 62 61 60 59 D8P D8N D7P D7N D6P D6N CLKOUTP CLKOUTN RLVDS OVSS D5P D5N D4P D4N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AVDD DNC DNC DNC DNC AVDD AVSS AVSS VINN VINP AVSS AVDD DNC DNC 19 20 21 22 23 24 25 26 27 28 29 30 31 32 15 16 17 18 VCM CLKDIV DNC DNC 33 34 35 36 D3P D3N D2P D2N 40 39 38 37 58 57 56 55 Connect Thermal Pad to AVSS |
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