ISLA112P25MREP datasheet(20/29 Pages) RENESAS

20 / 29 page

ISLA112P25M

FN7646 Rev 1.00

Page 20 of 29

November 17, 2011

Serial Peripheral Interface

A serial peripheral interface (SPI) bus is used to

facilitate configuration of the device and to optimize

performance. The SPI bus consists of chip select (CSB),

serial clock (SCLK) serial data output (SDO), and serial

data input/output (SDIO). The maximum SCLK rate is

equal to the ADC sample rate (fSAMPLE) divided by 16

for write operations and fSAMPLE divided by 66 for

reads. At fSAMPLE = 250MHz, maximum SCLK is

15.63MHz for writing and 3.79MHz for read operations.

There is no minimum SCLK rate.

The following sections describe various registers that

are used to configure the SPI or adjust performance or

functional parameters. Many registers in the available

address space (0x00 to 0xFF) are not defined in this

document. Additionally, within a defined register there

may be certain bits or bit combinations that are

reserved. Undefined registers and undefined values

within defined registers are reserved and should not be

selected. Setting any reserved register or value may

produce indeterminate results.

SPI Physical Interface

The serial clock pin (SCLK) provides synchronization for

the data transfer. By default, all data is presented on the

serial data input/output (SDIO) pin in three-wire mode.

The state of the SDIO pin is set automatically in the

communication protocol (described below). A dedicated

serial data output pin (SDO) can be activated by setting

0x00[7] high to allow operation in four-wire mode.

The SPI port operates in a half duplex master/slave

configuration, with the ISLA112P25MREP functioning as a

slave. Multiple slave devices can interface to a single

master in three-wire mode only, since the SDO output of

an unaddressed device is asserted in four-wire mode.

The chip-select bar (CSB) pin determines when a slave

device is being addressed. Multiple slave devices can be

written to concurrently, but only one slave device can be

FIGURE 36. SPI READ

(3 WIRE MODE)

(4 WIRE MODE)

R/W

A12

A11

A10

D1 D0

WRITING A READ COMMAND

READING DATA

tDHR

tDVR

SPI READ

tHI

tCLK

tLO

tDHW

tDSW

CSB

SCLK

SDIO

SDO

FIGURE 37. 2-BYTE TRANSFER

CSB

SCLK

SDIO

INSTRUCTION/ADDRESS

DATA WORD 1

DATA WORD 2

CSB STALLING

FIGURE 38. N-BYTE TRANSFER

CSB

SCLK

SDIO

INSTRUCTION/ADDRESS

DATA WORD 1

DATA WORD N

LAST LEGAL

CSB STALLING

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