ZSSC4151C Datasheet

© 2022 Renesas Electronics Corporation

4

March 25, 2020

1. Pin Assignments

In addition to tested die and wafer, the ZSSC4151C is available in a 24-QFN RoHS-conformant package (4

 4 mm; wettable flanks) and in a

16-TSSOP package (5.0 x 4.4 mm according to JEDEC MO-153) with an exposed pad. For details regarding die and wafers, refer to the

ZSSC4151C Technical Note – Die and Pad Dimensions, which is available on request (see last page for contact information).

Recommendation: On the printed circuit board (PCB), the land pattern of the exposed pad should be shorted to the solder pad of the VSSA pin.

1.1 Pin Layout for 24-QFN Package

Note: The backside of the 24-QFN package (exposed pad; see section 12) is electrically connected to VSSA. A solder connection to the exposed

pad of the 24-QFN package is not needed.

Figure 1. 24-QFN Pin Assignments – Top View

ZSSC4151C

18

TS2

17

TOP

16

TS1

15

BOT

13

BR1N

14

12

11

10

9

7

8

VSSE

1

VDDE

2

SCL

3

SDA

4

VDDA

6

VSSA

5

19

20

21

22

24

23

1.2 Pin Layout for 16-TSSOP Package

Note: The backside of the package 16-TSSOP (exposed pad; see section 12) is electrically connected to VSSA. A solder connection to the

exposed pad of the 16-TSSOP package is not needed.

Figure 2. 16-TSSOP Pin Assignments – Top View

BOT

TS1

TOP

n.c.

VSSE

SCL

SDA

2

1

3

TS2

VSSA

4

5

n.c.

6

7

15

16

14

13

12

11

10

VDDE

BR1N

BR1P

AOUT

8

9

VDDA

n.c.