MB91302ASLASHV301A datasheet(71/135 Pages) FUJI

71 / 135 page

MB91301 Series

PPG Timer

The PPG timer can output highly precise PWM waveforms efficiently.

The MB91301 series contains four channels of PPG timer.

• Features of the PPG Timer

• Each channel consists of a 16-bit down counter, a 16-bit data register with cycle setting buffer, a 16-bit compare

• The count clocks for the 16-bit down counter can be selected from the following four types :

Internal clock

φ, φ/4, φ/16, φ/64

• The counter is initialized to “FFFFH” at a reset or counter borrow.

• Each channel has a PPG output.

• Register outline

Cycle setting register: Reload data register with buffer

Duty setting register: Compare register with buffer

Transfer from the buffer takes place upon a counter borrow.

• Pin control overview

A duty match sets the pin control section to 1. (Preferential)

A counter borrow resets it to 0.

The output value fix mode is available, which can each output all "L" (or "H").

A polarity can also be specified.

• An interrupt request can be generated at a combination of the following events :

Activation of the PPG timer

Counter borrow (cycle match)

Duty match

Counter borrow (cycle match) or duty match

DMA transfer can be initiated by the above interrupt request.

• It is possible to set the simultaneous activation of two or more channels by means of software or another

interval timer.

Restarting during operation can also be set.

• The request level to be detected can be selected from among "rising edge", "falling edge", and "both edges".

MB91302A/V301A Datasheet(PDF) 71 Page - Fuji Electric