ICS8S73034I Data Sheet

LOW SKEW , ÷2, ÷4, ÷8 DIFFERENTIAL-TO-LVPECL CLOCK DIVIDER

ICS8S73034AMI REVISION A JUNE 8, 2011

14

©2011 Integrated Device Technology, Inc.

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS8S73034I.

Equations and example calculations are also provided.

1.

Power Dissipation.

The total power dissipation for the ICS8S73034I is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VCC = 3.8V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•

Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 45mA = 171mW

•

Power (outputs)MAX = 30.3mW/Loaded Output pair

If all outputs are loaded, the total power is 3 * 30.3mW = 90.9mW

Total Power_MAX (3.8V, with all outputs switching) = 171mW + 90.9mW = 261.9mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj =

θ

JA * Pd_total + TA

Tj = Junction Temperature

θ

JA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance

θ

JA must be used. Assuming no air flow and

a multi-layer board, the appropriate value is 100°C/W per Table 6B below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.262W * 100°C/W = 111.2°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 6A. Thermal Resistance θJA for 16 Lead SOIC Forced Convection

Table 6B. Thermal Resistance θJA for 16 Lead TSSOP Forced Convection

θ

JA by Velocity

Meters per Second

01

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

70.2°C/W

64.7°C/W

61.6°C/W

θ

JA by Velocity

Meters per Second

01

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

100.0°C/W

94.2°C/W

90.2°C/W