IDTTM

56-pin CK505 for Embedded Intel Systems

1614B—01/21/10

ICS9EPRS525

3

56-pin CK505 for Embedded Systems

Pin Description (continued)

PIN #

PIN NAME

TYPE

DESCRIPTION

25

SRCC3_LRS/CR#_D

I/O

Complementary clock of low power differential SRC clock pair with integrated 33 ohm Rs/ Clock Request control D for either SRC1 or SRC4 pair.

The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before

configuring this pin as a Clock Request Pin, the SRC output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC output is

disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CRD#_EN bit located in byte 5 of SMBUs

address space.

Byte 5, bit 1

0 = SRC3 enabled (default)

1= CRD# enabled. Byte 5, bit 0 controls whether CRD# controls SRC1 or SRC4 pair

Byte 5, bit 0

0 = CRD# controls SRC1 pair (default),

1= CRD# controls SRC4 pair

26

VDDSRCIO

PWR

Power supply for SRC outputs. 1.05V to 3.3V.

27

SRCT4_LRS

OUT

True clock of low power differential SRC clock pair with integrated 33 ohm Rs.

28

SRCC4_LRS

OUT

Complement clock of low power differential SRC clock pair with 33 ohm integrated Rs.

29

CPU_STOP#/SRCC5_LRS

I/O

Stops all CPUCLK, except those set to be free running clocks /

Complement clock of low power differential SRC pair with 33 ohm integrated Rs.

30

PCI_STOP#/SRCT5_LRS

I/O

Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by this input. / True clock of low power differential SRC pair

with integrated 33 ohm Rs.

31

VDDSRC

PWR

Supply for SRC PLL, 3.3V nominal

32

SRCC6_LRS

OUT

Complement clock of low power differential SRC clock pair with 33 ohm integrated Rs.

33

SRCT6_LRS

OUT

True clock of low power differential SRC clock pair with integrated 33 ohm Rs.

34

GNDSRC

PWR

Ground pin for the SRC outputs

35

SRCC7_LRS/CR#_E

I/O

Complement clock of differential push-pull SRC clock pair with 33 ohm integrated Rs. / Clock Request control E for SRC6 pair. The power-up default

is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the

SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be

set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space

Byte 6, bit 7

0 = SRC7# enabled (default)

1= CRE# enabled.

36

SRCT7_LRS/CR#_F

I/O

True clock of differential push-pull SRC clock pair/ Clock Request control 8 for SRC8 pair

The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock

Request Pin, the SR

37

VDDSRCIO

PWR

Power supply for SRC outputs. 1.05V to 3.3V.

38

CPUC2_ITP_LRS/SRCC8_LRS

OUT

Complement clock of low power differential CPU2/Complement clock of differential SRC pair. 33 ohm Rs is integrated. The function of this pin is

determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:

Pin 7 latched input Value

0 = SRC8#

1 = ITP#

39

CPUT2_ITP_LRS/SRCT8_LRS

OUT

True clock of low power differential CPU2/True clock of differential SRC pair. 33 ohm Rs is integrated. The function of this pin is determined by the

latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:

Pin 7 latched input Value

0 = SRC8

1 = ITP

40

NC

N/A

No Connect

41

VDDCPUIO

PWR

Power supply for CPU outputs, 1.05V to 3.3V.

42

CPUC1_F_LRS

OUT

Complementary clock of low power differential push-pull CPU output with integrated 33 ohm Rs. This CPU clock is free running during iAMT.

43

CPUT1_F_LRS

OUT

True clock of differential push-pull CPU clock pair with integrated 33 ohm Rs. This clock is free running during iAMT.

44

GNDCPU

PWR

Ground pin for the CPU outputs

45

CPUC0_LRS

OUT

Complement clock of low power differential CPU clock pair with integrated 33 ohm Rs.

46

CPUT0_LRS

OUT

True clock of low power differential CPU clock pair with integrated 33 ohm Rs.

47

VDDCPU

PWR

Supply for CPU PLL, 3.3V nominal

48

CK_PWRGD/PD#

IN

Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode

49

FSLB/TEST_MODE

IN

3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time

input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table.

50

GNDREF

PWR

Ground pin for the REF outputs.

51

X2

OUT

Crystal output, Nominally 14.318MHz

52

X1

IN

Crystal input, Nominally 14.318MHz.

53

VDDREF

PWR

Ref, XTAL power supply, nominal 3.3V

54

REF0/FSLC/TEST_SEL

I/O

14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.

/TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table

55

SDATA

I/O

Data pin for SMBus circuitry, 5V tolerant.

56

SCLK

IN

Clock pin of SMBus circuitry, 5V tolerant.