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THS8083CPZP Datasheet(PDF) 39 Page - Texas Instruments |
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THS8083CPZP Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 61 page ![]() 3–15 PWDN_REF Powers down internal top and bottom references for all channels (VREFT / VREFB). If powered down, enables user to supply external VREFT / VREFB references on corresponding pins. 0 = active (default) 1 = powered down PWDN_BGAP Powers down bandgap reference. If powered down, enables user to supply external VMID (input common mode voltage) on corresponding pin. 0 = active (default) 1 = powered down DTO_DIS Disables the DTO. Can be disabled when an external clock (EXT_ADCCLK) is used and the user does not intend to use the PLL output on DTOCLK3. When the PLL is active, it can be used as the clock source for the ADC channels or the ADC’s can still run from EXT_ADCCLK depending on the SEL_ADCCLK register setting. Note that when the DTO is enabled and the device is configured to use an external clock, the DTO clock is still available on the DTOCLK3 pin so it can be used as a general-purpose clock synthesizer for other parts in the system, possibly the display clock if this is different from the input pixel clock. Since the DTO is also used for internal clock generation, power should always be supplied to the PLL supply pins, even when the ADC sampling clock is fed from EXT_ADCCLK and DTO_DIS is active. 0 = active (default) 1 = powered down 3.2.44 Register Name: AUX_CTRL Subaddress: 31 (R/W) X MSB LSB X X CS_DIS TEST2 TEST1 TEST0 TACT CS_DIS Enables/disables the composite sync output on terminal CS/TEST1. The state of the CS output is also dependent on the clamp range (see section Composite Sync Slicer in functional description). 0 = enabled (default) 1 = disabled TEST[2..0] TACT This is for TI factory testing only and should not be changed from its default all 0 value. 3.2.45 Register Name: CH1_RDBK Subaddress: 32 (R) CH1_RDBK7 MSB LSB CH1_RDBK6 CH1_RDBK5 CH1_RDBK4 CH1_RDBK3 CH1_RDBK2 CH1_RDBK1 CH1_RDBK0 CH1_RDBK[7..0]: Readback register of ADC Channel 1 Default: (changed during operation) |
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