THS8083CPZP datasheet(19/61 Pages) TI

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2–5

The port is designed to operate from a master clock frequency of 14.31818 MHz, which is a standard frequency in

video applications: 4x the subcarrier frequency for NTSC. Many low-cost crystals are available for this frequency. The

default internal oscillator operates at 8x the master clock frequency, so operating frequency is about 114 MHz. This

setting of 8x, which is the value of the feedback divider in the analog PLL loop, is programmable (VCODIV register

value). The user can change this value when a master clock of a different frequency is connected. In this case care

should be taken to keep the internal high-frequency clock (i.e., master clock frequency x analog feedback divider)

lower than 120 MHz. The higher this internal frequency, the better the frequency resolution of the DTO.

When a crystal is used as the master clock source, it is not advised to use another frequency than the recommended

14.31818 MHz, since the internal oscillator circuitry is not production tested at other frequencies. If another master

clock is used, it is recommended to drive XTL1–MCLK by a direct clock signal. VCODIV should be programmed such

that the internal clock remains close to but less than 120 MHz.

14.31818 MHz

Phase-

Frequency

Detector

Loop

Filter

VCO

Programmable

Divider

VCODIV

VCOCLK

(To Digital PLL)

Figure 2–5. Analog PLL

2.6.2

Digital PLL

The digital PLL loop derives the ADC (pixel) clock frequency from the high-speed internal clock. A DTO will generate

an output frequency from a user-programmable DTO increment. To operate over the 13.5–80 MHz range, an extra

DTO clock output divider can be switched in. Appendix A shows the formula that relates the frequency of the internal

high-speed clock, the DTO increment value, and the DTO clock output divider to the PLL output frequency.

The PLL output, after the clock divider, is sent to the programmable feedback divider (TERM_CNT register value).

This value will typically be programmed to the number of total pixels per line for a given video/graphics format. The

output of this divider is then one input to the phase-frequency detector. Its other input is typically the horizontal sync

(HS) reference of a graphics/video signal. HS needs to be provided as a separate TTL/CMOS type signal to the

dedicated input terminal; See section 2.3 Composite Sync Slicer, to use the PLL in the case of input signals with a

composite sync. The polarity of HS is programmable (HS_POL register value).

Both HS and VS inputs on the THS8083 can accept a 3-V and a 5-V logic-compliant signal.

On the HS input, as on the VS input, a digital noise gate can be optionally switched in (HS_MS respectively VS_MS

they are interpreted as a valid HS and VS. This avoids having any spikes being interpreted as e.g. an active HS and

falsely updating the PLL.

The PFD produces a digital error value, signaling the phase/frequency difference between the HS input and the

divided PLL output clock. The integrated digital PLL loop filter subsequently filters this error value. This filter consists

of a proportional and integrator (accumulator) part. Gains of both parts are programmable (GAIN_N and GAIN_P

proportional or integrator portions of the filter, which translates into a wider capture range and faster acquisition but

also higher steady-state jitter.

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