BLC10G22XS-401AVT

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Product data sheet

Rev. 1 — 20 May 2022

4 of 14

BLC10G22XS-401AVT

Power LDMOS transistor

7.

Test information

7.1 Ruggedness in Doherty operation

The BLC10G22XS-401AVT is capable of withstanding a load mismatch corresponding to

VSWR = 10 : 1 through all phases under the following conditions: VDS =32V;

IDq =776 mA; VGS(amp)peak = 0.74 V; f = 2210 MHz; PL = 160 W (5 dB OBO); 1-carrier

W-CDMA; 3GPP test model 1; 64 DPCH; PAR = 9.6 dB at 0.01 % probability on CCDF.

7.2 Impedance information

[1]

ZS and ZL defined in Figure 1.

[2]

At 3 dB gain compression.

[1]

ZS and ZL defined in Figure 1.

[2]

At 3 dB gain compression.

Table 9.

Typical impedance of main device

Measured load-pull data of main device; IDq = 650 mA (main); VDS = 30 V; pulsed CW (tp = 100 s;

 =10%).

f

ZS [1]

ZL [1]

PL [2]



D

[2]

Gp [2]

(MHz)

(

)

(

)

(W)

(%)

(dB)

Maximum power load

2110

3.8

 j11.3

2.8

 j7.7

206

59.7

14.9

2140

4.6

 j12.0

2.8

 j7.7

205

59.6

14.9

2170

5.7

 j12.7

2.8

 j7.7

202

59.2

15.0

Maximum drain efficiency load

2110

3.7

 j11.6

6.0

 j5.3

137

70.0

17.1

2140

4.6

 j12.3

5.9

 j5.3

134

69.8

17.2

2170

5.7

 j13.0

5.3

 j5.0

133

69.2

17.2

Table 10.

Typical impedance of peak device

Measured load-pull data of peak device; IDq = 1085 mA (peak); VDS = 30 V; pulsed CW (tp =100 s;

 =10%).

f

ZS [1]

ZL [1]

PL [2]



D

[2]

Gp [2]

(MHz)

(

)

(

)

(W)

(%)

(dB)

Maximum power load

2110

4.2

 j9.5

6.3

 j6.8

305

57.7

15.6

2140

5.4

 j9.4

6.3

 j6.8

303

57.5

15.7

2170

6.7

 j8.7

6.3

 j6.8

300

57.3

15.8

Maximum drain efficiency load

2110

4.3

 j9.4

4.0

 j3.2

220

66.7

17.6

2140

5.6

 j9.1

4.0

 j3.2

214

66.4

17.8

2170

6.8

 j8.0

3.7

 j3.5

209

66.1

17.9