ICS871S1022EK November 2, 2017

3

©2017 Integrated Device Technology, Inc.

ICS871S1022 Datasheet

DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1, 17

VDD

Power

Core supply pins.

2

CLK

Input

Pulldown

Non-inverting differential clock input.

3

nCLK

Input

Pullup/

Pulldown

Inverting differential clock input. Internal resistor bias to VDD/2.

4VDD_XTAL

Power

Crystal oscillator supply pin.

5,

6

XTAL_IN,

XTAL_OUT

Input

Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the

input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal

circuit with a single-ended or differential reference clock.

7

CLK_SEL

Input

Pullup

Input source control pin and device operation control pin. See Table 3C.

LVCMOS/LVTTL interface levels.

8, 12, 20, 28

GND

Power

Power supply ground.

9, 16, 25, 32

VDDO

Power

Output power supply pins.

10, 11

QB0, nQB0

Output

Differential output pair. HCSL interface levels.

13

OEB

Input

Pullup

Output enable pin for QB, nQB[0:1] pins. When HIGH, the outputs are active.

When LOW, the outputs are in high-impedance state. See Table 3A.

LVCMOS/LVTTL interface levels.

14,15

QB1, nQB1

Output

Differential output pair. HCSL interface levels.

18, 19

N1, N0

Input

Pulldown

Output divider control pins. See Table 3D for additional information.

LVCMOS/LVTTL interface levels.

21

VDDA

Power

Analog supply pin.

22

SSC_EN

Input

Pulldown

SSC enable pin. See Table 3B. LVCMOS/LVTTL interface levels.

23

PLL_SEL

Input

Pullup

PLL Bypass control pin. LVCMOS/LVTTL interface levels.

24

IREF

Output

HCSL current reference resistor output. An external fixed precision resistor

(475

) from this pin to ground provides a reference current used for

differential current-mode Qx, nQx clock outputs.

26, 27

nQA1, QA1

Output

Differential output pair. HCSL interface levels.

29

OEA

Input

Pullup

Output enable pin for QA, nQA[0:1] pins. When HIGH, the outputs are active.

When LOW, the outputs are in a high-impedance state. See Table 3A.

LVCMOS/LVTTL interface levels.

30, 31

nQA0, QA0

Output

Differential output pair. HCSL interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

CIN

Input Capacitance

5pF

RPULLUP

Input Pullup Resistor

51

k



RPULLDOWN

Input Pulldown Resistor

51

k

