STM32H7 datasheet(169/357 Pages) STMICROELECTRONICS

169 / 357 page

DS12110 Rev 10

169/357

STM32H742xI/G STM32H743xI/G

Electrical characteristics (rev Y)

320

fTRIG

External trigger frequency

fADC = 36 MHz

3.6

MHz

16-bit resolution

1/fADC

VAIN(3) Conversion voltage range

VREF+

VCMIV

Common mode input

voltage

VREF/2−

10%

VREF/2

VREF/2+

10%

RAIN

External input impedance

㏀

CADC

Internal sample and hold

capacitor

tADCREG_

STUP

ADC LDO startup time

µs

tSTAB

ADC power-up time

LDO already started

conversion

cycle

tCAL

Offset and linearity

calibration time

165,010

1/fADC

tOFF_CAL Offset calibration time

1,280

tLATR

Trigger conversion latency

for regular and injected

channels without aborting

the conversion

CKMODE = 00

1.5

2.5

CKMODE = 01

CKMODE = 10

2.25

CKMODE = 11

2.125

tLATRINJ

Trigger conversion latency

for regular and injected

channels when a regular

conversion is aborted

CKMODE = 00

2.5

3.5

CKMODE = 01

CKMODE = 10

3.25

CKMODE = 11

3.125

Sampling time

1.5

810.5

tCONV

Total conversion time

(including sampling time)

N-bit resolution

tS + 0.5 + N/2

(9 to 648 cycles in 14-bit

mode)

1. Guaranteed by design.

2. These values are obtained using the following formula: fS = fADC/ tCONV ,

where fADC = 36 MHz and tCONV = 1,5 cycle sampling time + tSAR sampling time.

Refer to the product reference manual for the value of tSAR depending on resolution.

3. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA.

Table 87. ADC characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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