ADL5315

Rev. 0 | Page 16 of 20

EVALUATION BOARD

ADL5315

INPT

SREF

VPOS

COMM

1

3

6

VSET

2

4

7

NC

8

IOUT

5

RLIM

GND

SW1

R3

0

Ω

L1

0

Ω

C2

0.01

μF

C1

0.01

μF

C3

390pF

C4

OPEN

R5

OPEN

R2

10k

Ω

R4

4k

Ω

R1

100

Ω

Figure 35. Evaluation Board Schematic (Rev. A)

Table 4. Evaluation Board (Rev. A) Configuration Options

Component

Function

Default Conditions

VPOS, GND

Supply and ground connections.

Not applicable

INPUT, L1, C4

Input Interface: The evaluation board is configured to accept an input current at the

SMA connector labeled INPUT. Filtering of this current can be done using L1 and C4.

L1 = 0 Ω (size 0805)

C4 = open (size 00603)

R4, C3

Input Compensation. Provides essential HF compensation at the INPT pin.

C3 = 390 pF (size 0805)

R4 = 4.02 kΩ (size 0402)

SREF, VSET, SW1,

R1, R6, R7

INPT Bias Voltage. The dc voltage applied to VSET determines the voltage at INPT,

Opening SW1 allows for VSET to be driven externally via the SMA connector.

SW1 = closed

R1 = 100 Ω (size 0402)

R6 = R7 = 0 Ω (size 0402)

IOUT, R5

Output/Mirror Current Interface: The output current at the SMA connector labeled IOUT is

equal to the value at INPT. R5 allows a resistor to be installed for applications where a

scaled voltage referenced to IPD is desirable instead of a current.

R5 = open (size 0603)

R2

Current Limiting. An external resistor to VPOS sets the current limit at INPT from

R2 = 10 kΩ (size 0402)

C1, C2, R3

Supply Filtering/Decoupling.

C1 = 0.01 μF (size 0402)

C2 = 0.1 μF (size 0603)

R3 = 0 Ω (size 0805)

Figure 36. Component Side Layout

Figure 37. Component Side Silkscreen