TW3811 datasheet(13/20 Pages) RENESAS

13 / 20 page

TW3811

FN8284 Rev.1.00

Page 13 of 20

Nov 29, 2012

MII Mode B (PHY Emulation) Input Timing

MII Mode B (PHY Emulation) Output Timing

RMII Interface

Ethernet data is transferred via the MII or RMII interface. The

TW3811 is designed to work with any PHY with an RMII

interface, and has been tested with the IP101A (IC+) PHY in RMII

mode. The 50MHz RMII clock may be supplied by the external

PHY or by the TEST_IO pin (when RMII Clock Source = 1).

RMII Mode A (MAC Emulation) Input Timing

RMII Mode A (MAC Emulation) Output Timing

TABLE 4. MII MODE B (PHY EMULATION) INPUT TIMING

PARAMETER

DESCRIPTION

MIN

TYP

MAX UNIT

T4.1

TX_CLKB Period

1/fXTA

DCTX_CLKB

TX_CLKB Duty Cycle

T4.2

Data Setup Time

T4.3

Data Hold Time

TABLE 5. MII MODE B (PHY EMULATION) OUTPUT TIMING

PARAMETER

DESCRIPTION

MIN

TYP

MAX UNIT

T5.1

RX_CLKB Period

1/fXTA

DCRX_CLKB

RX_CLKB Duty Cycle

T5.2

Output Data Valid Delay

TX_CLKB

(output)

TX_D[3:0]B,

TX_ENB,

TX_ERB,

(inputs)

T4.1

T4.2

T4.3

RX_CLKB

(output)

RX_D[3:0]B,

RX_DVB,

RX_ERB

(outputs)

T5.1

T5.2

TABLE 6. RMII MODE A (MAC EMULATION) INPUT TIMING

PARAMETER

DESCRIPTION

MIN

TYP

MAX UNIT

T6.1

TX_CLKA Period

DCTX_CLKA

TX_CLKA Duty Cycle

T6.2

Data Setup Time

T6.3

Data Hold Time

TABLE 7. RMII MODE A (MAC EMULATION) OUTPUT TIMING

PARAMETER

DESCRIPTION

MIN

TYP

MAX UNIT

T7.1

TX_CLKA Period

DCTX_CLKA

TX_CLKA Duty Cycle

T7.2

Output Data Valid Delay

FIGURE 2. OPTIONAL USE OF TEST_IO AS RMII CLOCK SOURCE

MDC

MDIO

External

RMII

PHY

TW3811 in

RMII Mode

RX_DVA

RX_ERA

TX_ENA

TX_ERA

TX_CLKA

TX_D0A, TX_D1A

RX_CLKA

RX_D0A, RX_D1A

TEST_IO

(Only connect

if TW3811 is

supplying

50MHz clock)

TX_CLKA

(input,

reference)

RX_D[1:0]A,

RX_DVA,

RX_ERA,

(inputs)

6.1

T6.2

T6.3

TX_CLKA

(input,

reference)

TX_D[1:0]A,

TX_ENA,

TX_ERA

(outputs)

T7.1

T7.2

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