TW3811 datasheet(15/20 Pages) RENESAS

15 / 20 page

TW3811

FN8284 Rev.1.00

Page 15 of 20

Nov 29, 2012

I2C Serial Interface

The TW3811 supports a bidirectional bus oriented protocol. The

protocol defines any device that sends data onto the bus as a

transmitter and the receiving device as the receiver. The device

controlling the transfer is the master and the device being controlled

is the slave. The master always initiates data transfers and provides

the clock for both transmit and receive operations. Therefore, the

TW3811 operates as a slave device in all applications.

All communication over the I2C interface is conducted by sending

the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line can change only during SCL LOW

periods. SDA state changes during SCL HIGH are reserved for

indicating START and STOP conditions (see Figure 5). On

power-up of the TW3811 the SDA pin is in the input mode.

All I2C interface operations must begin with a START condition,

which is a HIGH to LOW transition of SDA while SCL is HIGH. The

TW3811 continuously monitors the SDA and SCL lines for the

START condition and does not respond to any command until this

condition is met (see Figure 5). A START condition is ignored

during the power-up sequence and during non-volatile write

cycles for the device.

All I2C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while SCL is

HIGH (see Figure 5). A STOP condition at the end of a read

operation, or at the end of a write operation places the device in

its standby mode. A STOP condition at the end of a write

operation to a non-volatile byte initiates an internal non-volatile

write cycle. The device enters its standby state when the internal,

non-volatile write cycle is completed.

An ACK, Acknowledge, is a software convention used to indicate

a successful data transfer. The transmitting device, either master

or slave, releases the SDA bus after transmitting eight bits.

During the ninth clock cycle, the receiver pulls the SDA line LOW

to acknowledge the reception of the eight bits of data (see

Figure 6).

The TW3811 responds with an ACK after recognition of a START

condition followed by a valid Identification Byte, and once again

after successful receipt of an Address Byte. The TW3811 also

responds with an ACK after receiving a Data Byte of a write

operation. The master must respond with an ACK after receiving

a Data Byte of a read operation.

A valid Identification Byte contains 0011 1 A1 A0 R/W as the

seven MSBs, where A0 = the logic level of the A0 pin, A1 = the

logic level of the A1 pin, and R/W is the bit that determines if the

next operation is a read or a write. The Read/Write bit is “1” for a

Read operation, and “0” for a Write operation (see Table 12).

Write Operation

A Write operation requires a START condition, followed by a valid

Identification Byte, a valid Address Byte, a Data Byte, and a STOP

condition. After each of the three bytes, the TW3811 responds

with an ACK.

STOP conditions that terminate write operations must be sent by

the master after sending at least 1 full data byte and its

associated ACK signal. If a STOP byte is issued in the middle of a

data byte, or before 1 full data byte + ACK is sent, then the

TW3811 resets itself without performing the write.

Read Operation

A Current Address Read operation is shown in Figure 8. It

consists of a minimum 2 bytes: a START followed by the ID byte

from the master with the R/W bit set to 1, then an ACK followed

by the data byte or bytes sent by the slave. The master

terminates the Read operation by not responding with an ACK

and then issuing a STOP condition. This operation is useful if the

master knows the current address and desires to read one or

more data bytes.

A Random Address Read operation consists of a three byte

“dummy write” instruction followed by a Current Address Read

operation (see Figure 6). The master initiates the operation

TABLE 11. RMII PASSTHROUGH MODE TIMING

PARAMETER

DESCRIPTION

MIN

TYP

MAX UNIT

T10.1

D to Q Setup Time

T10.2

D to Q Hold Time

FIGURE 4. RMII PASSTHROUGH MODE

RX_DVB

RX_DVA

RX_ERA

TX_ENA

TX_ERA

TX_CLKA

TX_DnA

RX_DnA

RX_CLKA

RX_ERB

TX_ENB

TX_ERB

TX_CLKB

TX_DnB

RX_DnB

RX_CLKB

External

PHY

External

MAC/SoC

TW3811 in

Passthrough

Mode

MDC

MDIO

TABLE 12. IDENTIFICATION BYTE FORMAT

Address Byte for a

Write

Address Byte for a Read

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

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