Data Sheet

ADMV8513

REGISTER DETAILS

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Rev. 0 | 24 of 31

Address: 0x014, Reset: 0x00, Name: FAST_LATCH_STATE

Table 22. Bit Descriptions for FAST_LATCH_STATE

Bits

Bit Name

Description

Reset

Access

7

RESERVED

Reserved.

0x0

R

[6:0]

FAST_LATCH_STATE

Fast Latch State. Reads back the internal state machine index for the fast latch LUT (SFL mode). This index

is the next location the internal state machine advances to, on the next CS rising edge. The internal state

machine index is set to the start index if the direction is set to increment, and the internal state machine index

is set to the stop index if the direction is set to decrement. Upon changes to the start index, stop index, and

direction, the index updates accordingly.

0x0

R

Address: 0x020, Reset: 0x00, Name: WR_FC

Table 23. Bit Descriptions for WR_FC

Bits

Bit Name

Description

Reset

Access

[7:0]

FC_LOAD_WR

Write Group: Center Frequency.

0x0

R/W

Address: 0x021, Reset: 0x00, Name: WR_BW

Table 24. Bit Descriptions for WR_BW

Bits

Bit Name

Description

Reset

Access

[7:0]

BW_LOAD_WR

Write Group: Bandwidth.

0x0

R/W

Address: 0x022, Reset: 0x00, Name: WR_MATCH

Table 25. Bit Descriptions for WR_MATCH

Bits

Bit Name

Description

Reset

Access

[7:0]

MATCH_LOAD_WR

Write Group: Match.

0x0

R/W