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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

Datasheet

Document Number: 249241

Revision Number: 007

Revision Date: August 28, 2003

Table 9. Intel® LXT9785/LXT9785E MDIO Control Interface Signals – PQFP

Pin/Ball

Designation

Symbol

Type1

Signal Description2,3,4

PQFP

PBGA

F3,

A10

MDIO0

MDIO1

I/O, TS, SL,

Management Data Input/Output.

Bidirectional serial data channel for communication

between the PHY and MAC or switch ASIC. Only

MDIO0 is used when 1x8 port sectionalization is

selected. In 2x4 port sectionalization mode, MDIO0

accesses ports 0-3 and MDIO1 accesses ports 4-7.

Refer to Figure 21 on page 140.

F1,

MDINT0

MDINT1

OD,TS, SL,

Management Data Interrupt.

When Register bit 18.1 = 1, an active Low output on this

Pin indicates status change. Only MDINT0 is used when

1x8 port sectionalization is selected.

In 2x4 port

sectionalization mode, MDINT0 is associated with ports

0-3 and MDINT1 is associated with ports 4-7. Refer to

Figure 21 on page 140.

E1,

B10

MDC0

MDC1

I, ST, ID

Management Data Clock.

Clock for the MDIO serial data channel. Maximum

frequency is 20 MHz. Only MDC0 is used when 1x8 port

sectionalization is selected. In 2x4 port

sectionalization mode, MDC0 clocks ports 0-3 register

accesses and MDC1 clocks ports 4-7 register accesses.

Refer to Figure 21 on page 140.

MDDIS

I, ST, ID

Management Disable.

When MDDIS is tied High, the MDIO port is completely

disabled and the Hardware Control Interface pins set

their respective bits at power up and reset.

When MDDIS is pulled Low at power up or reset, via the

internal pull-down resistor or by tieing it to ground, the

Hardware Control Interface Pins control only the initial

or “default” values of their respective register bits. After

the power-up/reset cycle is complete, bit control reverts

to the MDIO serial channel.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-

Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

3. MDIO[0:1] and MDINT[0:1] outputs are three-stated in H/W Power-Down mode and during H/W reset.

4. Supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,

where X is the register number (0-32) and Y is the bit number (0-15).

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