LXT9785 datasheet(43/226 Pages) INTEL

43 / 226 page

LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

Datasheet

Document Number: 249241

Revision Number: 007

Revision Date: August 28, 2003

AMDIX_EN

I, ST, IP

Auto MDIX Enable Default.

This pin is read at startup or reset. Its value at that time

is used to set the default state of Register bit 27.9 for

all ports. These register bits can be read and

overwritten after startup / reset. Refer to Table 40 on

page 119.

When active (High), automatic MDI crossover (MDIX)

(regardless of segmentation) is selected for all ports.

When inactive (Low) MDIX is selected according to the

MDIX pin.

MDIX

I, ID, ST

MDIX Select Default.

This pin is read at startup or reset. Its value at that time

is used to set the default state of Register bit 27.8 for

all ports. These register bits can be read and

overwritten after startup / reset. Refer to Table 40,

“Intel® LXT9785/LXT9785E MDIX Selection” on

page 119.

When AMDIX_EN is active this pin is ignored.

When AMDIX_EN is inactive, all ports are forced to the

MDI or the MDIX function regardless of segmentation.

If this pin is active (high), MDI crossover (MDIX) is

selected. If this pin is inactive, non-crossover MDI

mode is set.

This pin is shared with RMII-RxER0. An external pull-

up resistor (see applications section for value) can be

used to set MDIX active while RxER0 is three-stated

during H/W reset. If no pull-up is used, the default

MDIX state is set inactive via the internal pull-down

resistor. Do not tie this pin directly to VCCIO (vs. using

a pull-up) in non-RMII modes.

L2,

L3,

CFG_3

CFG_2

CFG_1

I, ST, ID

Global Port Configuration Defaults 1-3.

These pins are read at startup or reset. Their value at

that time is used to set the default state of register bits

shown in Table 42, “Intel® LXT9785/9785E Global

Hardware Configuration Settings” on page 129 for all

ports. These register bits can be read and overwritten

after startup / reset.

When operating in Hardware Control Mode, these pins

provide configuration control options for all the ports

(refer to page 129 for details).

173

M14

G_FX/TP

I, ST, ID

Global FX/TP Enable Default.

This pin is read at startup or reset. Its value at that time

is used to set the default state of Register bit 16.0 for

all ports. These register bits can be read and

overwritten after startup / reset. Refer to Table 92, “Port

Configuration Register (Address 16, Hex 10)” on page 207.

This input selects whether all the ports are defaulted to

TP vs. FX mode.

Table 13. Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP (Sheet 3 of 4)

Pin/Ball

Designation

Symbol

Type1

Signal Description2

PQFP

PBGA

1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =

Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal

Pull-Down.

2. The IP/ID resistors are disabled during hardware power-down mode.

LXT9785 Datasheet(PDF) 43 Page - Intel Corporation

LXT9785 Datasheet(HTML) 43 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL