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CS5535 Datasheet(PDF) 400 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 400 Page - National Semiconductor (TI) |
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400 / 555 page  www.national.com 400 Revision 0.8 5.13 DIRECT MEMORY ACCESS REGISTER DESCRIPTIONS The registers for the Direct Memory Access (DMA) are divided into three sets: • Standard GeodeLink Device MSRs (Shared with DIVIL, see Section 5.6.1 on page 299.) • DMA Specific MSRs • DMA Native Registers The MSRs are accessed via the RDMSR and WRMSR pro- cessor instructions. The MSR address is derived from the perspective of the CPU Core. See Section 3.2 "CS5535 MSR Addressing" on page 53 for more details on MSR addressing. All MSRs are 64 bits, however, the DMA Specific MSRs (summarized in Table 5-52) are called out as 16 bits. The DMA module treats writes to the upper 48 bits (i.e., bits [63:16]) of the 64-bit MSRs as don’t cares and always returns 0 on these bits. The Native registers associated with the DMA module are summarized in Table 5-53 and accessed as I/O Addresses. The reference column in the summary tables point to the page where the register maps and bit descriptions are listed. Table 5-52. DMA Specific MSRs Summary MSR Address Type Register Name Reset Value Reference 51400040h R/W DMA Mapper (DMA_MAP) 0000h Page 403 51400041h RO DMA Shadow Channel 0 Mode (DMA_SHDW_CH0) 00xxh Page 404 51400042 RO DMA Shadow Channel 1 Mode (DMA_SHDW_CH1) 00xxh Page 404 51400043 RO DMA Shadow Channel 2 Mode (DMA_SHDW_CH2) 00xxh Page 404 51400044 RO DMA Shadow Channel 3 Mode (DMA_SHDW_CH3) 00xxh Page 404 51400045h RO DMA Shadow Channel 4 Mode (DMA_SHDW_CH4] 00xxh Page 404 51400046h RO DMA Shadow Channel 5 Mode (DMA_SHDW_CH5) 00xxh Page 404 51400047h RO DMA Shadow Channel 6 Mode (DMA_SHDW_CH6) 00xxh Page 404 51400048h RO DMA Shadow Channel 7 Mode (DMA_SHDW_CH7) 00xxh Page 404 51400049h RO DMA Shadow Mask (DMA_MSK_SHDW) 00FFh Page 405 Table 5-53. DMA Native Registers Summary I/O Address Type Width (Bits) Register Name Reset Value Reference 000h R/W 8 Slave DMA Channel 0 Memory Address (DMA_CH0_ADDR_BYTE) xxh Page 405 001h R/W 8 Slave DMA Channel 0 Transfer Count (DMA_CH0_CNT_BYTE) xxh Page 406 002h R/W 8 Slave DMA Channel 1 Memory Address (DMA_CH1_ADDR_BYTE) xxh Page 405 003h R/W 8 Slave DMA Channel 1 Transfer Count (DMA_CH1_CNT_BYTE) xxh Page 406 004h R/W 8 Slave DMA Channel 2 Memory Address (DMA_CH2_ADDR_BYTE) xxh Page 405 005h R/W 8 Slave DMA Channel 2 Transfer Count (DMA_CH2_CNT_BYTE) xxh Page 406 |
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