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CS5535 Datasheet(PDF) 411 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 411 Page - National Semiconductor (TI) |
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411 / 555 page  Revision 0.8 411 www.national.com DMA Register Descriptions (Continued) 5.13.2.13 DMA Channel [7:4] Status / Command Master DMA Channel [7:4] Status (DMA_CH7:4_STS) Master DMA Channel [7:4] Command (DMA_CH7:4_CMD) DMA_CH[x]_CNT_BYTE Bit Descriptions Bit Name Description 7:0 DMA_CH_CNT_BYTE DMA Channel Transfer Count. Read/write in two successive bus cycles, low byte first. I/O Address 0D0h Type R Reset Value 00h DMA_CH7:4_STS Register Map 76543 210 DMA_CH7_RQ DMA_CH6_RQ DMA_CH5_RQ DMA_CH4_RQ DMA_CH7_TC DMA_CH6_TC DMA_CH5_TC DMA_CH4_TC DMA_CH7:4_STS Bit Descriptions Bit Name Description 7 DMA_CH7_RQ Channel 7 DMA Request. 0: Not pending; 1: Pending. 6 DMA_CH6_RQ Channel 6 DMA Request. 0: Not pending; 1: Pending. 5 DMA_CH5_RQ Channel 5 DMA Request. 0: Not pending; 1: Pending. 4 DMA_CH4_RQ Channel 4 DMA Request. 0: Not pending; 1: Pending. 3 DMA_CH7_TC Channel 7 Terminal Count. 0: Count not reached; 1: Count reached. 2 DMA_CH6_TC Channel 6 Terminal Count. 0: Count not reached; 1: Count reached. 1 DMA_CH5_TC Channel 5 Terminal Count. 0: Count not reached; 1: Count reached. 0 DMA_CH4_TC Channel 4 Terminal Count. 0: Count not reached; 1: Count reached. I/O Address 0D0h Type W Reset Value xxh DMA_CH7:4_CMD Register Map 76543 210 DACK_SENSE DREQ_SENSE WR_TIMING PR_MODE TM_MODE DMA_DIS RSVD DMA_CH7:4_CMD Bit Descriptions Bit Name Description 7 DACK_SENSE DACK Sense. 0: Active low; 1: Active high. 6 DREQ_SENSE DREQ Sense. 0: Active high; 1: Active low. 5 WR_TIMING Write Timing. 0: Late write; 1: Extended write. 4 PR_MODE Priority Mode. 0: Fixed priority; 1: Rotating priority. 3 TM_MODE Timing Mode. 0: Normal timing; 1: Compressed timing. |
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