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CS5535 Datasheet(PDF) 413 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 413 Page - National Semiconductor (TI) |
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413 / 555 page ![]() Revision 0.8 413 www.national.com DMA Register Descriptions (Continued) 5.13.2.16 Master DMA Channel [7:4] Mode (DMA_CH7:4_MODE) 5.13.2.17 Master DMA Channel [7:4] Clear Byte Pointer (DMA_CH7:4_CLR_PNTR) I/O Address 0D6h Type WO Reset Value xxh DMA_CH7:4_MODE Register Map 76543 210 TRANS_MODE ADDR_DIR AUTO_INIT TRANS_TYPE DMA_CH_SEL DMA_CH7:4_MODE Bit Descriptions Bit Name Description 7:6 TRANS_MODE Data Transfer Mode. 00: Demand. 10: Block. 01: Single. 11: Cascade. 5 ADDR_DIR Address Direction. 0: Increment; 1: Decrement. 5 AUTO_INIT Auto-Initialization Enable. 0: Disabled; 1: Enabled. 3:2 TRANS_TYPE Transfer Type. 00: Verify. 10: Memory read. 01: Memory write. 11: Reserved 1:0 DMA_CH_SEL DMA Channel Select. 00: Channel 4. 10: Channel 6. 01: Channel 5. 11: Channel 7. I/O Address 0D8h Type WO Reset Value xxh DMA_CH7:4_CLR_PNTR Register Map 76543 210 CLR_PNTR (DUMMY_VAL) DMA_CH7:4_CLR_PNTR Bit Descriptions Bit Name Description 7:0 CLR_PNTR Clear Pointer. A write with any data (dummy value) resets high/low byte pointer for Channels [7:4] memory address and terminal count registers. |
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