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M58BW16F Datasheet(PDF) 28 Page - STMicroelectronics |
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M58BW16F Datasheet(HTML) 28 Page - STMicroelectronics |
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28 / 81 page  Bus operations M58BW16F, M58BW32F 28/81 3.2.2 Synchronous Burst Read Suspend During a Synchronous Burst Read operation it is possible to suspend the operation, freeing the data bus for other higher priority devices. A valid Synchronous Burst Read operation is suspended when both Output Enable and Burst Address Advance are High, VIH. The Burst Address Advance going High, VIH, stops the burst counter and the Output Enable going High, VIH, inhibits the data outputs. The Synchronous Burst Read operation can be resumed by setting Output Enable Low. 1. X = Don't Care, VIL or VIH. 2. M15 = 0, Bit M15 is in the Burst Configuration Register. 3. R = Rising Edge. 3.3 Burst Configuration Register The Burst Configuration Register is used to configure the type of bus access that the memory will perform. The Burst Configuration Register is set through the Command Interface and will retain its information until it is re-configured, the device is reset, or the device goes into Reset/Power- Down mode. The Burst Configuration Register bits are described in Table 8. They specify the selection of the burst length, burst type, burst X and Y latencies and the Read operation. Refer to Figure 4 for examples of synchronous burst configurations. 3.3.1 Read Select Bit (M15) The Read Select bit, M15, is used to switch between asynchronous and synchronous Bus Read operations. When the Read Select bit is set to ’1’, Bus Read operations are asynchronous; when the Read Select but is set to ’0’, Bus Read operations are synchronous. On reset or power-up the Read Select bit is set to’1’ for asynchronous accesses. 3.3.2 Standby Disable Bit (M14) The Standby Disable Bit, M14, is used to disable the Standby mode. When the Standby bit is ‘1’, the device will not enter Standby mode when Chip Enable goes High, VIH. Table 7. Synchronous Burst Read bus operations Bus Operation Step E G GD RP KL B A0-Amax DQ0-DQ31 Synchronous Burst Read(2) Address Latch VIL VIH XVIH R(3) VIL X Address Input Read VIL VIL VIH VIH R(3) VIH VIL Data Output Read Suspend VIL VIH XVIH XVIH VIH High Z Read Resume VIL VIL VIH VIH R(3) VIH VIL Data Output Burst Address Advance VIL VIH XVIH R(3) VIH VIL High Z Read Abort, E VIH XX VIH XXX High Z Read Abort, RP XX X VIL XXX High Z |
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