PI7C8150ANDE datasheet(87/111 Pages) PERICOM

87 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 87 of 111

APRIL 2006 – Revision 1.1

Bit

Function

Type

Description

Secondary

Master Timeout

R/W

Set’s the maximum number of PCI clocks the bridge will wait for an

initiator on the secondary to repeat a delayed transaction request. The

counter starts right after the delayed transaction is at the front of the

queue. If the master has not repeated at least once before the counter

expires, the bridge discards the transaction from the queue.

0: 2

PCI clocks

1: 2

PCI clocks

Reset to 0

Master Timeout

Status

R/WC

This bit is set to 1 when either the primary master timeout counter or

secondary master timeout counter expires.

Reset to 0

Discard Timer

P_SERR_L

enable

R/W

This bit is set to 1 and P_SERR_L is asserted when either the

primary discard timer or the secondary discard timer expire.

Reset to 0

31-28

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0.

14.1.29

DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h

Bit

Function

Type

Description

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0

Memory Write

Disconnect

Control

R/W

Controls when the bridge (as a target) disconnects memory write

transactions.

0: memory write disconnects at 4KB aligned address boundary

1: memory write disconnects at cache line aligned address boundary

Reset to 0

3:2

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0.

Secondary Bus

Prefetch Disable

R/W

Controls the bridge’s ability to prefetch during upstream memory

read transactions.

0: The bridge prefetches and does not forward byte enable bits during

upstream memory reads.

1: The bridge requests only 1 DWORD from the target and forwards

read byte enable bits during upstream memory reads.

Reset to 0

Live Insertion

Mode

R/W

Enables hardware control of transaction forwarding.

0: GPIO[3] has no effect on the I/O, memory, and master enable bits

1: If GPIO[3] is set to input mode, this bit enables GPIO[3] to mask

I/O enable, memory enable and master enable bits to 0. PI7C8150A

will stop accepting I/O and memory transactions as a result.

Reset to 0

7:6

Reserved

R/O

Reserved. Returns 0 when read. Reset to 0

Chip Reset

R/WR

Controls the chip and secondary bus reset.

0: PI7C8150A is ready for operation

1: Causes PI7C8150A to perform a chip reset

06-0057

PI7C8150ANDE Datasheet(PDF) 87 Page - Pericom Semiconductor Corporation

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