UPD61052GD-LML datasheet(63/108 Pages) RENESAS

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Data Sheet S15082EJ4V0DS

µPD61051, 61052

4.8

Transfer Error Handling

4.8.1

Transfer error handling 1

It is the error handling of DMA-ERR which occurs when interrupting the transfers (the host CPU

→ the instruction

RAM of internal CPU transfer, the host CPU

→ SDRAM transfer (SSD, SDW), the external ROM → SDRAM transfer

and the external ROM

→ the instruction RAM of internal CPU transfer)

Transfer error

handling 1

Host CPU

→ SDRAM transfer

release

Transfer mode register

(20H)

← 00H setting

Set destination address register

(24H to 26H)

to unused area of SDRAM

Host CPU

→ SDRAM transfer

Transfer mode register

(20H)

← 02H setting

Interrupt register 0

(30H)

← 01H setting

Transfer counter register

(27H to 29H)

← 04H setting

Transfer data register

(3FH)

← Dummy data

Clear the transfer error

Interrupt register 0 (30H)

← 04H setting

Return

CINT?

Interrupt register 0

(30H): 01H

All data

writing ending?

UPD61052GD-LML Datasheet(PDF) 63 Page - Renesas Technology Corp

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