UPD63335GA-9EU datasheet(13/58 Pages) RENESAS

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Data Sheet S15003EJ6V0DS

µPD63335

1.6

Digital Interfaces

The

µPD63335 uses two different interfaces to connect to an external host processor (such as a CPU or sound

controller). One is the serial command interface that controls the

µPD63335, and the other is the serial data interface

that is used for data input and output.

Figure 1-4. Digital Interfaces

1.6.1

Serial command interface

When accessing the

µPD63335 from an external host processor, use the clocked serial interface (MSCLK,

MSWDT, MSRDT).

Transfer of addresses begins in sync with the rising edge of MSCLK, immediately after the RESET signal goes

from low level to high level. Addresses consist of eight bits, of which bit 7 indicates the read/write attribute for

access.

When a “1” is transferred to bit 7 in the address, a read operation is performed. After an address is input via the

MSWDT pin, the contents of the corresponding register are output via the MSRDT pin.

When a “0” is transferred to bit 7 in the address, a write operation is performed. Once the address is sent from the

host processor, 8-bit data is written.

The

µPD63335 uses the data to check for bit drift in the serial command interface so as to ensure accurate control

from the host processor.

When communication is being performed correctly, the D6 address bit of all the registers except the warm reset

the occurrence of bit displacement among the serial command interface bits. For details of the SICK bit, refer to

2.1.1 Serial command interface check bit (SICK).

LRCLK

BIT_CLK

MSCLK

MSWDT

MSRDT

PD63335

Host processor

Serial command interface

Serial data interface

MSCLK

RESET

MSWDT

(Input)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

MSRDT

(Output)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Address

Write data

Read data

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