CS8900A_01 datasheet(78/137 Pages) CIRRUS

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DS271PP4

CS8900A

Crystal LAN™ ISA Ethernet Controller

CIRRUS LOGIC PRODUCT DATASHEET

5.0 OPERATION

5.1 Managing Interrupts and Servicing the

Interrupt Status Queue

The Interrupt Status Queue (ISQ) is used by the

CS8900A to communicate Event reports to the host

processor. Whenever an event occurs that triggers

an enabled interrupt, the CS8900A sets the appro-

priate bit(s) in one of five registers, maps the con-

tents of that register to the ISQ, and drives the

selected interrupt request pin high (if an earlier in-

terrupt is waiting in the queue, the interrupt request

pin will already be high). When the host services

the interrupt, it must first read the ISQ to learn the

nature of the interrupt. It can then process the inter-

rupt (the first read to the ISQ causes the interrupt

request pin to go low.)

Three of the registers mapped to the ISQ are event

registers: RxEvent (Register 4), TxEvent (Register

8), and BufEvent (Register C). The other two reg-

isters are counter-overflow reports: RxMISS (Reg-

ister 10) and TxCOL (Register 12). There may be

more than one RxEvent report and/or more than

one TxEvent report in the ISQ at a time. However,

there may be only one BufEvent report, one Rx-

MISS report and one TxCOL report in the ISQ at a

time.

Event reports stored in the ISQ are read out in the

order of priority, with RxEvent first, followed by

TxEvent, BufEvent, RxMiss, and then TxCOL.

The host only needs to read from one location to get

the interrupt currently at the front of the queue. In

Memory Mode, the ISQ is located at PacketPage

base + 0120h. In I/O Mode, it is located at I/O base

+ 0008h. Each time the host reads the ISQ, the bits

in the corresponding register are cleared and the

next report in the queue moves to the front.

When the host starts reading the ISQ, it must read

and process all Event reports in the queue. A read-

out of a null word (0000h) indicates that all inter-

rupts have been read.

The ISQ is read as a 16-bit word. The lower six bits

(0 through 5) contain the register number (4, 8, C,

10, or 12). The upper ten bits (6 through F) contain

the register contents. The host must always read the

entire 16-bit word.

The active interrupt pin (INTRQx) is selected via

the Interrupt Number register (PacketPage base +

22h). As an additional option, all of the interrupt

pins can be 3-Stated using the same register. see

Section 4.3 on page 41.

An event triggers an interrupt only when the En-

ableIRQ bit of the Bus Control register (bit F of

ed an interrupt, the first read of the ISQ makes the

INTRQ output pin go low (inactive). INTRQ re-

mains low until the null word (0000h) is read from

the ISQ, or for 1.6us, whichever is longer.

5.2 Basic Receive Operation

5.2.0.1 Overview

Once an incoming packet has passed through the

analog front end and Manchester decoder, it goes

through the following three-step receive process:

1) Pre-Processing

2) Temporary Buffering

3) Transfer to Host

Figure 20 shows the steps in frame reception.

As shown in the figure, all receive frames go

through the same pre-processing and temporary

buffering phases, regardless of transfer method

Once a frame has been pre-processed and buffered,

it can be accessed by the host in either Memory or

I/O space. In addition, the CS8900A can transfer

receive frames to host memory via host DMA. This

section describes receive frame pre-processing and

Memory

and

I/O

space

receive

operation.

Section 5.4 on page 89 through Section 5.5 on

page 92 describe DMA operation.

CS8900A Datasheet(PDF) 78 Page - Cirrus Logic

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