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VCTA25201B-R33MS6 Datasheet(PDF) 36 Page - Richtek Technology Corporation |
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VCTA25201B-R33MS6 Datasheet(HTML) 36 Page - Richtek Technology Corporation |
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36 / 50 page  RTQ2134-QA Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 36 Register Address 0x35 Register Name FLT_MASKBUCK3 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write RW RW RW RW R R R R Bits Name Description Bit 7 FLT_BUCK3MASKPG Masking Buck3 power good detection signal. 0 : Pass internal logic output to INT pin. 1 : Mask internal logic output to INT pin. Bit 6 BUCK3INTACT Write this bit to "1" to ensure Buck3 INT function normally. "0" is reserved for Richtek internal use only. Bit 5 FLT_BUCK3MASKOV Masking Buck3 over-voltage detection signal. 0 : Pass internal logic output to INT pin. 1 : Mask internal logic output to INT pin. Bit 4 FLT_BUCK3MASKUV Masking Buck3 under-voltage detection signal. 0 : Pass internal logic output to INT pin. 1 : Mask internal logic output to INT pin. Bit 3 to Bit 0 Reserved Reserved bits Register Address 0x37 Register Name FLT_BUCK1_CTRL Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 1 1 0 0 Read/Write R R R R RW R R R Bits Name Description Bit 7 to Bit 4 Bit 2 to Bit 0 Reserved Reserved bits Bit 3 FLT_BUCK1_ CTRLUV Latch or hiccup protection behavior when Buck1 suffers UV detection. 0 : UV Shutdown 1 : UV Hiccup Register Address 0x38 Register Name FLT_BUCK2_CTRL Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 1 1 0 0 Read/Write R R R R RW R R R Bits Name Description Bit 7 to Bit 4 Bit 2 to Bit 0 Reserved Reserved bits Bit 3 FLT_BUCK2_ CTRLUV Latch or hiccup protection behavior when Buck2 suffers UV detection. 0 : UV Shutdown 1 : UV Hiccup |
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