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ES9820 Datasheet(PDF) 57 Page - ESS Technology,Inc

Part # ES9820
Description  32-bit High-Performance 2-Channel ADC
PDF  117 Pages
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Manufacturer  ESS [ESS Technology,Inc]
Direct Link  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9820 Datasheet(HTML) 57 Page - ESS Technology,Inc

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CONFIDENTIAL ADVANCE INFORMATION 0.3
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM
57
ES9820 Product Datasheet
Register 22-21: DITHER MASK
Bits
[15:0]
Default
16'hFFFF
Bits
Mnemonic
Description
[15:0]
DITHER_MASK
Mask off the LSB's of PCM data output.
16'h0000 => Quantized to 16 bits
16'h8000 => Quantized to 17 bits
16'hC000 => Quantized to18 bits
16'hE000 => Quantized to 19 bits
16'hF000 => Quantized to 20 bits
16'hF800 => Quantized to 21 bits
16'hFC00 => Quantized to 22 bits
16'hFE00 => Quantized to 23 bits
16'hFF00 => Quantized to 24 bits
16'hFF80 => Quantized to 25 bits
16'hFFC0 => Quantized to 26 bits
16'hFFE0 => Quantized to 27 bits
16'hFFF0 => Quantized to 28 bits
16'hFFF8 => Quantized to 29 bits
16'hFFFC => Quantized to 30 bits
16'hFFFE => Quantized to 31 bits
16'hFFFF => Quantized to 32 bits (default)
others: Reserved
Register 23: FS GEN PHASE CONTROL
Bits
[7]
[6:0]
Default
1'b0
7'd4
Bits
Mnemonic
Description
[7]
DSD_SYNC_TO_1FS
In DSD mode, when enabled, DSD logic is sync to an 1FS
signal input from GPIO2. When not enabled, DSD logic is
sync to DSD clock input from GPIO1.
1'b0: DSD logic is sync to DSD clock input from GPIO1
(default)
1'b1: DSD logic is sync to 1FS signal input from GPIO2
[6:0]
RESERVED
NA
Register 26-24: RESERVED



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