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ES9820 Datasheet(PDF) 67 Page - ESS Technology,Inc

Part # ES9820
Description  32-bit High-Performance 2-Channel ADC
PDF  117 Pages
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Manufacturer  ESS [ESS Technology,Inc]
Direct Link  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9820 Datasheet(HTML) 67 Page - ESS Technology,Inc

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CONFIDENTIAL ADVANCE INFORMATION 0.3
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM
67
ES9820 Product Datasheet
Register 63: ADC CH1 CONFIG 1
Bits
[7:4]
[3]
[2]
[1]
[0]
Default
4'd0
1'b0
1'b0
1'b0
1'b0
Bits
Mnemonic
Description
[7:4]
ADC_INT_SEL_CH1
ADC Integrator Control
•
Program to 4'b1011 for optimum performance
[3]
ADC_EN_FB_CH1
Enable ADC 1 feedback path, active high
•
1'b0: Disabled (default)
•
1'b1: Enabled
[2]
RESERVED
NA
[1]
ADC_EN_INT_CH1
Enable for INT for Channel 1. Default is 0, INT is not enabled.
•
Set to 1'b1 to enable.
[0]
ADC_EN_CH1
Enable for Comparator and logic for Channel 1. Default is 0,
Comparator and logic are not enabled
•
Set to 1'b1 to enable.
Register 64: ADC CH1 CONFIG 2
Bits
[7:5]
[4:3]
[2]
[1]
[0]
Default
3'd0
2'd0
1'b0
1'b0
1'b0
Bits
Mnemonic
Description
[7:5]
ADC_COMP_SEL_CH1
Sets the gain of Comparator of Channel 1.
•
Program to 3'b001 for optimum performance
[4:3]
ADC_SUM_SEL_CH1
Sets the bandwidth of the summing amplifier for Channel 1.
•
Program to 2'b11 for optimum performance
[2]
ADC_USE_DITHER_EXT_CH1
Enable the external dither for Channel 1.
•
Default value is 0.
[1]
ADC_USE_DITHER_CH1
Enable the dither for Channel 1.
•
Default value is 0, dither is not enabled
[0]
ADC_USE_STATE_CH1
Use state as logic output for Channel 1.
•
Default value is 0.



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