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ES9820 Datasheet(PDF) 92 Page - ESS Technology,Inc

Part # ES9820
Description  32-bit High-Performance 2-Channel ADC
PDF  117 Pages
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Manufacturer  ESS [ESS Technology,Inc]
Direct Link  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9820 Datasheet(HTML) 92 Page - ESS Technology,Inc

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CONFIDENTIAL ADVANCE INFORMATION 0.3
ES9820 Product Datasheet
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM
92
Synchronous Slave Interface Registers
Register 192: SOFT RESET
Bits
[7]
[6:0]
Default
1'b0
7'd0
Bits
Mnemonic
Description
[7]
AO_SOFT_RESET
Performs soft reset to digital core except for the PLL
REGISTERS.
[6:0]
RESERVED
NA
Register 193: CLK SELECT
Bits
[7:3]
[2:1]
[0]
Default
5'd0
2'd0
1'b0
Bits
Mnemonic
Description
[7:3]
RESERVED
NA
[2:1]
SEL_SYSCLK_IN
Selects digital core and ADC clock source when
EN_ANA_CLKIN is set.
•
2'd0: XTAL (default)
•
2'd1: MCLK
•
2'd2: ACLK
•
2'd3: PLL
[0]
EN_ANA_CLKIN
Enables clock outputs to the digital core and ADC.
•
1'b0: Disabled (default)
•
1'b1: Enabled
Register 194: ADC CLOCK DIVIDE
Bits
[7:2]
[1:0]
Default
6'd0
2'd0
Bits
Mnemonic
Description
[7:2]
RESERVED
NA
[1:0]
SEL_CLK_DIV
Sets ADC clock rate:
2'd0: full-rate (Divide by 1)
2'd1: 1/2 rate (Divide by 2)
2'd2: 1/4 rate (Divide by 4)
2'd3: 1/8 rate (Divide by 8)
Register 203-195: RESERVED



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