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ES9822PRO Datasheet(PDF) 42 Page - ESS Technology,Inc |
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ES9822PRO Datasheet(HTML) 42 Page - ESS Technology,Inc |
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42 / 126 page  0.3 ES9822 PRO Product Datasheet ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 42 Register Map Addr (Hex) Addr (Dec) Register 7 6 5 4 3 2 1 0 0x0 0 SYS CONFIG SOFT_RESET OUTPUT_SEL RESERVED ENABLE_2X_M ODE RESERVED MONO_MODE RESERVED 0x1 1 ADC CLOCK CONFIG1 ENABLE_DATA_IN _CH2B ENABLE_DATA_IN _CH1B ENABLE_DATA_IN_ CH2A ENABLE_DAT A_IN_CH1A ENABLE_ADC_ CH2B ENABLE_ADC_CH 1B ENABLE_ADC_ CH2A ENABLE_ADC_CH1 A 0x2 2 ADC CLOCK CONFIG2 RESERVED SELECT_ADC_HALF SELECT_ADC_NUM 0x3 3 ADC CLOCK CONFIG3 OUTPUT2_SEL FORCE_OUTPUT2 INVERT_FIRS T_CLK_SAMP LE2 SELECT_IADC_ HALF SELECT_IADC_NUM 0x4 4 ADC CLOCK CONFIG4 FORCE_PHASE_C LK_IADC PHASE_CLK_IADC RESERVED INVERT_SAMPL E_CLOCK_CH2 INVERT_SAMPLE_C LOCK_CH1 0x5 5 RAW DATA AND SPDIF CONFIG SELECT_RAW_DATA_NUM RAW_DATA_CLK_DI V2 RAW_DATA_D DR ENABLE_RAW_ DATA_CLK ENABLE_SPDIF_C LK RESERVED 0x6 6 DSD CONFIG RESERVED DSD_DDR DSD_MASTER _MODE RESERVED ENABLE_DSD_ CLK_CH2 ENABLE_DSD_CLK_ CH1 0x7 7 DSD AND I2S/TDM MASTER CLK CONFIG MASTER_WS_SCALE DSD_CLK_DIV 2 SELECT_DSD_NUM 0x8 8 I2S/TDM MASTER MODE CONFIG MASTER_BCK_DI V1 MASTER_WS_IDL E MASTER_FRAME_LENGTH MASTER_WS_P ULSE_MODE MASTER_BCK_IN VERT MASTER_WS_I NVERT MASTER_MODE_EN ABLE 0x9 9 I2S/TDM MASTER CLK CONFIG SELECT_I2S_TDM _HALF SELECT_I2S_TDM_NUM 0xA 10 TDM CONFIG1 TDM_BIT_DELAY TDM_VALID_EDG E TDM_LJ ENABLE_TDM_CLK 0xB 11 TDM CONFIG2 TDM_GPIO456 TDM_CASCADE TDM_LENGTH TDM_CH_NUM 0xC 12 TDM SLOT CONFIG CH1 RESERVED TDM_SLOT_SEL_CH1 0xD 13 TDM SLOT CONFIG CH2 RESERVED TDM_SLOT_SEL_CH2 0xE 14 RESERVED RESERVED 0xF 15 RESERVED RESERVED 0x10 16 RESERVED RESERVED 0x11 17 RAW DATA MAPPING RESERVED RAW_DATA_MAPPING_CH2 RAW_DATA_MAPPING_CH1 0x12 18 PCM DATA OUTPUT MAPPING RESERVED OUTPUT_MAPPING_CH2 OUTPUT_MAPPING_CH1 0x13 19 DSD DATA OUTPUT MAPPING RESERVED DSD_MAPPING_CH2 DSD_MAPPING_CH1 0x14 20 TPDF DITHER LEVEL RESERVED DITHER_SCALE 0x15 21 DITHER MASK DITHER_MASK 0x16 22 DITHER MASK DITHER_MASK 0x17 23 FS GEN PHASE CONTROL DSD_SYNC_TO_1 FS FS_PHASE 0x18- 0x1A 24-26 RESERVED RESERVED 0x1B 27 INTERRUPT RESERVED INTERRUPT_CLEAR _CH2_CLIP_DETEC TION INTERRUPT_ CLEAR_CH1_ CLIP_DETECT ION RESERVED INTERRUPT_MA SK_CH2_CLIP_ DETECTION INTERRUPT_MASK_ CH1_CLIP_DETECTI ON 0x20- 0x1C 32-28 SPDIF CONFIG SPDIF_CS 0x21 33 DSD DITHER SCALE AND SYNC CONTROL SYNC_POSEDGE _FRAME DISABLE_SYNC_ REF FORCE_FIR_SYNC DSD_DITHER_SCALE 0x22 34 SYNC CONTROL AUTO_ADC_CLKD IV_SYNC AUTO_CLK_IADC_ PHASE_SYNC AUTO_DSD_PHASE _SYNC AUTO_WS_PH ASE_SYNC AUTO_ICG_EN_ SYNC AUTO_ICG_SYNC AUTO_FIR_SYN C AUTO_FS_SYNC 0x23 35 ASP1 CONFIG RESERVED SELECT_ASP1_NUM ENABLE_ASP1_CLK |
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