ES9842PRO datasheet(50/167 Pages) ESS

Part #	ES9842PRO

Description	32-bit High-Performance 4-Channel ADC

PDF	167 Pages

Scroll/Zoom	100%

Manufacturer	ESS [ESS Technology,Inc]

Direct Link	http://www.esstech.com

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CONFIDENTIAL ADVANCE INFORMATION

ES9842 PRO Product Datasheet

VERSION 0.5

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

Figure 11 - Audio Interface Timing Requirements

MCLK edge to BCK edge

The ES9842PRO has a phase relationship requirement between MCLK (System Clock) and BCK (Bit Clock). The internal

ADC_CLK (which must be 24.576/22.5792MHz) is derived from the provided MCLK. It is important to make sure the internal

ADC_CLK does not transition during the serial data transitions. To achieve this, follow the MCLK to BCK timing outlined

below.

Figure 12 - 45/49MHz MCLK with BCK Phase Relationship

Symbol

MCLK [MHz]

Minimum Maximum Unit

BCK “↓” to MCLK “↓”

tBFMF

49.152 / 45.1584

MCLK “↓” to BCK “↓”

tMFBF

Table 24 – Timing relationship for 45/49MHz MCLK & BCK

ES9842PRO Datasheet(PDF) 50 Page - ESS Technology,Inc