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P5DF081UA/T1AD2060 Datasheet(PDF) 7 Page - NXP Semiconductors |
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P5DF081UA/T1AD2060 Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 40 page ![]() NXP Semiconductors P5DF081_SDS MIFARE secure access module SAM AV2 7 Pinning information 7.1 Pinning 001aam116 C1 VCC C5 GND C2 RST_N C6 IO3 C3 CLK_N C7 IO1 C4 n.c. C8 IO2 Figure 2. Pin configuration PCM1.1 7.2 Pinning 1 VSS n.c. IO3 n.c. IO1 LB IO2 DM VCC LA RSTN n.c. n.c. n.c. CLK DP 8 7 6 5 4 3 2 24 17 18 19 20 21 22 23 aaa-005250 P5DF081 Transparent top view terminal 1 index area Remark: Central pad is isolated. Figure 3. Pin configuration HVQFN32 7.3 Pin description ISO/IEC 7816 MIFARE SAM AV2 Pad Symbol Symbol Pad Description C1 VCC VCC C1 power supply voltage input C2 RST RST_N C2 reset input, active LOW C3 CLK CLK_N C3 clock input C4 reserved n.c. C4 n.c. C5 GND GND C5 ground (reference voltage) input C6 VPP IO3 C6 used for I2C communication to RC52x or RC663 (SCLK) Table 3. Pin description PCM 1.1 MIFARE SAM AV2 P5DF081_SDS All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product short data sheet Rev. 3.3 — 13 September 2023 7 / 40 |
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