Resource

Member Code

D5

D7

D9

Receiver

84

120

140

PCIe Hard IP Block

2

2

2

Hard Memory Controller

2

2

2

Related Information

True LVDS Buffers in Devices, I/O Features in Cyclone V Devices

Provides the number of LVDS channels in each device package.

Package Plan

Table 9.

Package Plan for Cyclone V GT Devices

Transceiver counts shown are for transceiver ≤5 Gbps . 6 Gbps transceiver channel count support depends on

the package and channel usage. For more information about the 6 Gbps transceiver channel count, refer to the

Cyclone V Device Handbook Volume 2: Transceivers.

Member

Code

M301

(11 mm)

M383

(13 mm)

M484

(15 mm)

U484

(19 mm)

GPIO

XCVR

GPIO

XCVR

GPIO

XCVR

GPIO

XCVR

D5

129

4

175

6

—

—

224

6

D7

—

—

—

—

240

3

240

6

D9

—

—

—

—

—

—

240

5

Member

Code

F484

(23 mm)

F672

(27 mm)

F896

(31 mm)

F1152

(35 mm)

GPIO

XCVR

GPIO

XCVR

GPIO

XCVR

GPIO

XCVR

D5

240

6

336

6

—

—

—

—

D7

240

6

336

9 (6)

480

9 (6)

—

—

D9

224

6

336

9 (6)

480

12 (7)

560

12 (7)

Related Information

6.144-Gbps Support Capability in Cyclone V GT Devices, Cyclone V Device Handbook

Volume 2: Transceivers

Provides more information about 6 Gbps transceiver channel count.

(6) If you require CPRI (at 6.144 Gbps) and PCIe Gen2 transmit jitter compliance, Intel

recommends that you use only up to three full-duplex transceiver channels for CPRI, and up

to six full-duplex channels for PCIe Gen2. The CMU channels are not considered full-duplex

channels.

(7) If you require CPRI (at 6.144 Gbps) and PCIe Gen2 transmit jitter compliance, Intel

recommends that you use only up to three full-duplex transceiver channels for CPRI, and up

to eight full-duplex channels for PCIe Gen2. The CMU channels are not considered full-duplex

channels.

Cyclone V Device Overview

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Cyclone V Device Overview

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