5CEBA2F13C6SC datasheet(26/37 Pages) INTEL

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Figure 10.

Device Chip Overview for Cyclone V GX and GT Devices

The figure shows a Cyclone V FPGA with transceivers. Different Cyclone V devices may have a different

floorplans than the one shown here.

I/O, LVDS, and Memory Interface

Hard Memory Controller

Core Logic Fabric and MLABs

Variable-Precision DSP Blocks

M10K Internal Memory Blocks

Transceiver

PMA

Transceiver

PMA

Transceiver

PMA

Hard

PCS

Hard

PCS

Hard

PCS

Transceiver

Individual Channels

PMA Features

To prevent core and I/O noise from coupling into the transceivers, the PMA block is

isolated from the rest of the chip—ensuring optimal signal integrity. For the

transceivers, you can use the channel PLL of an unused receiver PMA as an additional

transmit PLL.

Table 22.

PMA Features of the Transceivers in Cyclone V Devices

Features

Capability

Backplane support

Driving capability up to 6.144 Gbps

PLL-based clock recovery

Superior jitter tolerance

Programmable deserialization and word

alignment

Flexible deserialization width and configurable word alignment pattern

Equalization and pre-emphasis

• Up to 14.37 dB of pre-emphasis and up to 4.7 dB of equalization

• No decision feedback equalizer (DFE)

Ring oscillator transmit PLLs

614 Mbps to 6.144 Gbps

Input reference clock range

20 MHz to 400 MHz

Transceiver dynamic reconfiguration

Allows the reconfiguration of a single channel without affecting the operation of

other channels

Cyclone V Device Overview

683694 | 2018.05.07

Cyclone V Device Overview

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