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AT83SND2CMP3B Datasheet(PDF) 147 Page - ATMEL Corporation |
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AT83SND2CMP3B Datasheet(HTML) 147 Page - ATMEL Corporation |
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147 / 241 page  147 4341F–MP3–03/06 AT8xC51SND2C/MP3B may reset the data controller and its internal state machine by setting and clearing the DCR bit in MMCON2 register. This time-out may be disarmed after receiving 8 data (F1FI flag set) or after receiving end of frame (EOFI flag set) in case of block length less than 8 data (1, 2 or 4). 18.6.4.3 Data Reading Data is read from the FIFO by reading to MMDAT register. Each time one FIFO becomes full (F1FI or F2FI set), user is requested to flush this FIFO by reading 8 data. Figure 18-18. Data Stream Reception Flows Data Stream Reception FIFO Full? F1FI or F2FI = 1? FIFO Reading read 8 data from MMDAT No More Data To Receive? a. Polling mode Data Stream Initialization Data Stream Reception ISR FIFO Reading read 8 data from MMDAT Send STOP Command No More Data To Receive? b. Interrupt mode FIFO Full? F1FI or F2FI = 1? Unmask FIFOs Full F1FM = 0 F2FM = 0 Send STOP Command Mask FIFOs Full F1FM = 1 F2FM = 1 |
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