AT83SND2CMP3B datasheet(150/241 Pages) ATMEL

150 / 241 page

150

4341F–MP3–03/06

AT8xC51SND2C/MP3B

18.8

Registers

Table 18-8.

MMCON0 Register

MMCON0 (S:E4h) – MMC Control Register 0

Reset Value = 0000 0000b

543

210

DRPTR

DTPTR

CRPTR

CTPTR

MBLOCK

DFMT

RFMT

CRCDIS

Bit Number

Bit

Mnemonic

Description

DRPTR

Data Receive Pointer Reset Bit

Set to reset the read pointer of the data FIFO.

Clear to release the read pointer of the data FIFO.

DTPTR

Data Transmit Pointer Reset Bit

Set to reset the write pointer of the data FIFO.

Clear to release the write pointer of the data FIFO.

CRPTR

Command Receive Pointer Reset Bit

Set to reset the read pointer of the receive command FIFO.

Clear to release the read pointer of the receive command FIFO.

CTPTR

Command Transmit Pointer Reset Bit

Set to reset the write pointer of the transmit command FIFO.

Clear to release the read pointer of the transmit command FIFO.

3MBLOCK

Multi-block Enable Bit

Set to select multi-block data format.

Clear to select single block data format.

2DFMT

Data Format Bit

Set to select the block-oriented data format.

Clear to select the stream data format.

1RFMT

Response Format Bit

Set to select the 48-bit response format.

Clear to select the 136-bit response format.

CRCDIS

CRC7 Disable Bit

Set to disable the CRC7 computation when receiving a response.

Clear to enable the CRC7 computation when receiving a response.

AT83SND2CMP3B Datasheet(PDF) 150 Page - ATMEL Corporation

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