AT89LP4052-20PI datasheet(22/90 Pages) ATMEL

22 / 90 page

3547F–MICRO–6/06

AT89LP2052/LP4052

a control bit in the Special Function Register TCON. GATE is in TMOD. The 13-bit register con-

sists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate

and should be ignored. Setting the run flag (TR1) does not clear the registers. See Figure 15-1.

Figure 15-1. Timer/Counter 1 Mode 0: Variable Width Counter

Mode 0 operation is the same for Timer 0 as for Timer 1, except that TR0, TF0 and INT0 replace

the corresponding Timer 1 signals in Figure 15-1. There are two different GATE bits, one for

Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

15.2

Mode 1

In Mode 1 the Timers are configured for 16-bit auto-reload. The Timer register is run with all 16

bits. The 16-bit reload value is stored in the high and low reload registers (RH1/RL1). The clock

is applied to the combined high and low timer registers (TH1/TL1). As clock pulses are received,

the timer counts up: 0000H, 0001H, 0002H, etc. An overflow occurs on the FFFFH-to-0000H

transition, upon which the timer register is reloaded with the value from RH1/RL1 and the over-

flow flag bit in TCON is set. See Figure 15-2. The reload registers default to 0000H, which gives

the full 16-bit timer period compatible with the standard 8051. Mode 1 operation is the same for

Timer/Counter 0.

Figure 15-2. Timer/Counter 1 Mode 1: 16-bit Auto-Reload

OSC

T1 Pin

TR1

GATE

INT1 Pin

TL1

(8 Bits)

Control

Interrupt

C/T = 0

C/T = 1

PSC1

TH1

(8 Bits)

TF1

OSC

T1 Pin

TR1

GATE

INT1 Pin

TL1

(8 Bits)

Control

Interrupt

C/T = 0

C/T =1

TH1

(8 Bits)

TF1

RL1

(8 Bits)

RH1

(8 Bits)

Reload

AT89LP4052-20PI Datasheet(PDF) 22 Page - ATMEL Corporation

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